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* [gcc(refs/users/meissner/heads/work119)] Allow vec_extract to load vector registers.
@ 2023-04-19 19:48 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-19 19:48 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9b276947c58e0e4e5b9b8e29d01e3c95b33c7864
commit 9b276947c58e0e4e5b9b8e29d01e3c95b33c7864
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 15:48:06 2023 -0400
Allow vec_extract to load vector registers.
2023-04-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute
(vsx_extract_<mode>_load): Allow vec_extract of integer types with a
constant element number to load into vector registers. Allow splitting
before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ebc986fc6ac..cac0bda2b2c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,6 +223,12 @@
(V8HI "v")
(V4SI "wa")])
+;; Mode attribute to give the isa constraint for accessing Altivec registers
+;; with vector extract and insert operations.
+(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
+ (V8HI "p8v")
+ (V4SI "p7v")])
+
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3951,23 +3957,29 @@
}
[(set_attr "type" "mfvsr")])
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
+;; number. If the element number is 0, we don't need to do a load immediate
+;; operation. Likewise for GPRs with offsettable loads, we can fold the offset
+;; into the address. For loading to vector registers, we are limited to X-FORM
+;; memory addresses. We need TARGET_POWERPC64 because we are creating a DI
+;; base register temporary.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")
- (set_attr "length" "8")])
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,8,4,8")
+ (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow vec_extract to load vector registers.
@ 2023-04-20 23:43 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-20 23:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cdf017b6ed76f571efa5bdfd0ffd1de7a2678895
commit cdf017b6ed76f571efa5bdfd0ffd1de7a2678895
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 20 19:42:24 2023 -0400
Allow vec_extract to load vector registers.
2023-04-20 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute
(vsx_extract_<mode>_load): Allow vec_extract of integer types with a
constant element number to load into vector registers. Allow splitting
before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ebc986fc6ac..63f31980806 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,6 +223,12 @@
(V8HI "v")
(V4SI "wa")])
+;; Mode attribute to give the isa constraint for accessing Altivec registers
+;; with vector extract and insert operations.
+(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
+ (V8HI "p9v")
+ (V4SI "p8v")])
+
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3951,23 +3957,29 @@
}
[(set_attr "type" "mfvsr")])
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
+;; number. If the element number is 0, we don't need to do a load immediate
+;; operation. Likewise for GPRs with offsettable loads, we can fold the offset
+;; into the address. For loading to vector registers, we are limited to X-FORM
+;; memory addresses. We need TARGET_POWERPC64 because we are creating a DI
+;; base register temporary.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")
- (set_attr "length" "8")])
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,8,4,8")
+ (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow vec_extract to load vector registers.
@ 2023-04-19 18:51 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-19 18:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5d283240e71a33664d2ebc4c03009d1676ef7c2e
commit 5d283240e71a33664d2ebc4c03009d1676ef7c2e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 14:51:07 2023 -0400
Allow vec_extract to load vector registers.
2023-04-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute
(vsx_extract_<mode>_load): Allow vec_extract of integer types with a
constant element number to load into vector registers.
Diff:
---
gcc/config/rs6000/vsx.md | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0e681844243..533216321c4 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,6 +223,12 @@
(V8HI "v")
(V4SI "wa")])
+;; Mode attribute to give the isa constraint for accessing Altivec registers
+;; with vector extract and insert operations.
+(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
+ (V8HI "p8v")
+ (V4SI "p7v")])
+
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3951,23 +3957,27 @@
}
[(set_attr "type" "mfvsr")])
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number.
+;; If the element number is 0, we don't need to do a load immediate operation.
+;; Likewise for GPRs with offsettable loads, we can fold the offset into the
+;; address. For vector registers, we are limited to X-FORM memory addresses.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode)"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")
- (set_attr "length" "8")])
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,8,4,8")
+ (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 3+ messages in thread
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