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* [gcc(refs/users/meissner/heads/work119)] Fold sign or zero convert into vsx_extract from memory.
@ 2023-04-19 22:16 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-19 22:16 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a9d7cf178f1cc73ed1e92374251d6c8edd1a7520
commit a9d7cf178f1cc73ed1e92374251d6c8edd1a7520
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 18:16:19 2023 -0400
Fold sign or zero convert into vsx_extract from memory.
This patch folds sign or zero convert operations into vsx_extract from memory
where the element number is constant.
2023-04-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (VSX_EXTRACT_ISIGN): New mode attribute.
(vsx_extract_<mode>_load_to_udi): New insn.
(vsx_extract_<mode>_load_to_sdi): New insn.
(vsx_extract_v8hi_load_to_<su>si): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 71 ++++++++++++++++++++++
| 22 +++++++
| 37 +++++++++++
| 37 +++++++++++
4 files changed, 167 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index cac0bda2b2c..9be15b02af2 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -207,6 +207,10 @@
(define_mode_iterator VSX_EXTRACT_I2 [V16QI V8HI])
(define_mode_iterator VSX_EXTRACT_I4 [V16QI V8HI V4SI V2DI])
+;; Iterator for vector extract/insert of small integer vectors that can be sign
+;; extended with the load.
+(define_mode_iterator VSX_EXTRACT_ISIGN [V8HI V4SI])
+
(define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b")
(V8HI "h")
(V4SI "w")])
@@ -3981,6 +3985,73 @@
(set_attr "length" "4,4,8,4,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
+;; and zero extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ (zero_extend:DI
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,8,4,8")
+ (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
+;; and sign extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_load_to_sdi"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ (sign_extend:DI
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,12,8,12")
+ (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI element from memory with a constant element number
+;; and zero or sign extend it to SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_<su>si"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,v,v")
+ (any_extend:SI
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_7_operand" "0,n,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:SI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], HImode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,12,8,12")
+ (set_attr "isa" "*,*,*,p9v,p9v")])
+
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..a392e4322bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold the sign/extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e81ab4954ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold the sign/extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..3c834a77948
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold the sign/extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Fold sign or zero convert into vsx_extract from memory.
@ 2023-04-20 23:44 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-20 23:44 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e0efcf05e60994e325a8a76515b27482f0d9dc2b
commit e0efcf05e60994e325a8a76515b27482f0d9dc2b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 20 19:44:32 2023 -0400
Fold sign or zero convert into vsx_extract from memory.
This patch folds sign or zero convert operations into vsx_extract from memory
where the element number is constant.
2023-04-20 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (VSX_EXTRACT_ISIGN): New mode attribute.
(vsx_extract_<mode>_load_to_udi): New insn.
(vsx_extract_<mode>_load_to_sdi): New insn.
(vsx_extract_v8hi_load_to_<su>si): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 71 ++++++++++++++++++++++
| 22 +++++++
| 37 +++++++++++
| 37 +++++++++++
4 files changed, 167 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 63f31980806..dadd44ffed8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -207,6 +207,10 @@
(define_mode_iterator VSX_EXTRACT_I2 [V16QI V8HI])
(define_mode_iterator VSX_EXTRACT_I4 [V16QI V8HI V4SI V2DI])
+;; Iterator for vector extract/insert of small integer vectors that can be sign
+;; extended with the load.
+(define_mode_iterator VSX_EXTRACT_ISIGN [V8HI V4SI])
+
(define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b")
(V8HI "h")
(V4SI "w")])
@@ -3981,6 +3985,73 @@
(set_attr "length" "4,4,8,4,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
+;; and zero extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ (zero_extend:DI
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,8,4,8")
+ (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
+;; and sign extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_load_to_sdi"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ (sign_extend:DI
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,12,8,12")
+ (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI element from memory with a constant element number
+;; and zero or sign extend it to SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_<su>si"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,v,v")
+ (any_extend:SI
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_7_operand" "0,n,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:SI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], HImode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,12,8,12")
+ (set_attr "isa" "*,*,*,p9v,p9v")])
+
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..a392e4322bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold the sign/extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e81ab4954ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold the sign/extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..3c834a77948
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold the sign/extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Fold sign or zero convert into vsx_extract from memory.
@ 2023-04-19 20:06 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-19 20:06 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cf36f3bd3617da5e088e10129dfe9deaf679fb2d
commit cf36f3bd3617da5e088e10129dfe9deaf679fb2d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 16:06:23 2023 -0400
Fold sign or zero convert into vsx_extract from memory.
This patch folds sign or zero convert operations into vsx_extract from memory
where the element number is constant.
2023-04-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (VSX_EXTRACT_ISIGN): New mode attribute.
(vsx_extract_<mode>_load_to_udi): New insn.
(vsx_extract_<mode>_load_to_sdi): New insn.
(vsx_extract_v8hi_load_to_<su>si): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 71 ++++++++++++++++++++++
| 22 +++++++
| 37 +++++++++++
| 37 +++++++++++
4 files changed, 167 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index cac0bda2b2c..9be15b02af2 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -207,6 +207,10 @@
(define_mode_iterator VSX_EXTRACT_I2 [V16QI V8HI])
(define_mode_iterator VSX_EXTRACT_I4 [V16QI V8HI V4SI V2DI])
+;; Iterator for vector extract/insert of small integer vectors that can be sign
+;; extended with the load.
+(define_mode_iterator VSX_EXTRACT_ISIGN [V8HI V4SI])
+
(define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b")
(V8HI "h")
(V4SI "w")])
@@ -3981,6 +3985,73 @@
(set_attr "length" "4,4,8,4,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
+;; and zero extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ (zero_extend:DI
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,8,4,8")
+ (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
+;; and sign extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_load_to_sdi"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ (sign_extend:DI
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,12,8,12")
+ (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI element from memory with a constant element number
+;; and zero or sign extend it to SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_<su>si"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,v,v")
+ (any_extend:SI
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_7_operand" "0,n,n,0,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:SI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], HImode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "4,4,12,8,12")
+ (set_attr "isa" "*,*,*,p9v,p9v")])
+
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..f3cfb933789
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target vsx } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold the sign/extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..79cfba6f7f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target vsx } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold the sign/extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..e03ab6893a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target vsx } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold the sign/extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
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