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* [gcc(refs/users/meissner/heads/work119)] Fold conversion to float into V4SI vsx_extract from memory.
@ 2023-04-19 22:18 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-19 22:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1f703846588021750e825e3a187c9da5de5042a2
commit 1f703846588021750e825e3a187c9da5de5042a2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 18:18:37 2023 -0400
Fold conversion to float into V4SI vsx_extract from memory.
This patch folds conversion to floating point of vsx_extract from memory of V4SI
elements where the element number is constant. This code optimizes things so it
will load the integer with LFIWAX or LFIWZX directly into a vector register
rather than loading it into a GPR and doing a direct move operation.
2023-04-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (SIGN_ZERO_EXTEND): New mode attribute.
(vsx_extract_v4si_load_to_<uns><mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 32 ++++++++++++++++++
| 38 ++++++++++++++++++++++
2 files changed, 70 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9be15b02af2..4ed577a9e6c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -251,6 +251,10 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
+;; Whether to use SIGN or ZERO when depending on the floating point conversion.
+(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND")
+ (unsigned_float "ZERO_EXTEND")])
+
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -4051,6 +4055,34 @@
(set_attr "length" "4,4,12,8,12")
(set_attr "isa" "*,*,*,p9v,p9v")])
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode or DFmode using either signed or unsigned conversion.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
+ [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
+ (any_float:SFDF
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
+ (clobber (match_scratch:DI 3 "=&b,&b"))
+ (clobber (match_scratch:DI 4 "=f,v"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 4)
+ (match_dup 5))
+ (set (match_dup 0)
+ (float:SFDF (match_dup 4)))]
+{
+ if (GET_CODE (operands[4]) == SCRATCH)
+ operands[4] = gen_reg_rtx (DImode);
+
+ rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+ operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")
+ (set_attr "isa" "*,p8v")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..91e85bf5a5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,38 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and convert the value to float, and double by loading the value
+ directly into a vector register, and not loading up the GPRs first. */
+
+#include <altivec.h>
+
+float
+extract_float_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
+}
+
+float
+extract_float_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
+}
+
+double
+extract_double_uns_v4si_3 (vector unsigned int *p)
+{
+ return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Fold conversion to float into V4SI vsx_extract from memory.
@ 2023-04-20 23:46 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-20 23:46 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ba652394f48752ab4d65588eca1f67d46d0a768b
commit ba652394f48752ab4d65588eca1f67d46d0a768b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 20 19:46:10 2023 -0400
Fold conversion to float into V4SI vsx_extract from memory.
This patch folds conversion to floating point of vsx_extract from memory of V4SI
elements where the element number is constant. This code optimizes things so it
will load the integer with LFIWAX or LFIWZX directly into a vector register
rather than loading it into a GPR and doing a direct move operation.
2023-04-20 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (SIGN_ZERO_EXTEND): New mode attribute.
(vsx_extract_v4si_load_to_<uns><mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 32 ++++++++++++++++++
| 38 ++++++++++++++++++++++
2 files changed, 70 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index dadd44ffed8..bb06abceb00 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -251,6 +251,10 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
+;; Whether to use SIGN or ZERO when depending on the floating point conversion.
+(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND")
+ (unsigned_float "ZERO_EXTEND")])
+
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -4051,6 +4055,34 @@
(set_attr "length" "4,4,12,8,12")
(set_attr "isa" "*,*,*,p9v,p9v")])
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode or DFmode using either signed or unsigned conversion.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
+ [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
+ (any_float:SFDF
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
+ (clobber (match_scratch:DI 3 "=&b,&b"))
+ (clobber (match_scratch:DI 4 "=f,v"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 4)
+ (match_dup 5))
+ (set (match_dup 0)
+ (float:SFDF (match_dup 4)))]
+{
+ if (GET_CODE (operands[4]) == SCRATCH)
+ operands[4] = gen_reg_rtx (DImode);
+
+ rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+ operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")
+ (set_attr "isa" "*,p8v")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..91e85bf5a5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,38 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and convert the value to float, and double by loading the value
+ directly into a vector register, and not loading up the GPRs first. */
+
+#include <altivec.h>
+
+float
+extract_float_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
+}
+
+float
+extract_float_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
+}
+
+double
+extract_double_uns_v4si_3 (vector unsigned int *p)
+{
+ return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Fold conversion to float into V4SI vsx_extract from memory.
@ 2023-04-19 22:04 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-19 22:04 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3b8c02815ac3d9672dbe743499e90f9742921568
commit 3b8c02815ac3d9672dbe743499e90f9742921568
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 18:03:55 2023 -0400
Fold conversion to float into V4SI vsx_extract from memory.
This patch folds conversion to floating point of vsx_extract from memory of V4SI
elements where the element number is constant. This code optimizes things so it
will load the integer with LFIWAX or LFIWZX directly into a vector register
rather than loading it into a GPR and doing a direct move operation.
2023-04-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (SIGN_ZERO_EXTEND): New mode attribute.
(vsx_extract_v4si_load_to_<uns><mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 32 ++++++++++++++++++
| 38 ++++++++++++++++++++++
2 files changed, 70 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9be15b02af2..4ed577a9e6c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -251,6 +251,10 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
+;; Whether to use SIGN or ZERO when depending on the floating point conversion.
+(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND")
+ (unsigned_float "ZERO_EXTEND")])
+
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -4051,6 +4055,34 @@
(set_attr "length" "4,4,12,8,12")
(set_attr "isa" "*,*,*,p9v,p9v")])
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode or DFmode using either signed or unsigned conversion.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
+ [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
+ (any_float:SFDF
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
+ (clobber (match_scratch:DI 3 "=&b,&b"))
+ (clobber (match_scratch:DI 4 "=f,v"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 4)
+ (match_dup 5))
+ (set (match_dup 0)
+ (float:SFDF (match_dup 4)))]
+{
+ if (GET_CODE (operands[4]) == SCRATCH)
+ operands[4] = gen_reg_rtx (DImode);
+
+ rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+ operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")
+ (set_attr "isa" "*,p8v")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..91e85bf5a5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,38 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and convert the value to float, and double by loading the value
+ directly into a vector register, and not loading up the GPRs first. */
+
+#include <altivec.h>
+
+float
+extract_float_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
+}
+
+float
+extract_float_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
+}
+
+double
+extract_double_uns_v4si_3 (vector unsigned int *p)
+{
+ return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Fold conversion to float into V4SI vsx_extract from memory.
@ 2023-04-19 20:53 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-19 20:53 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c33c0f8ce847479281360086f7f5f4482dae3a45
commit c33c0f8ce847479281360086f7f5f4482dae3a45
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 16:52:27 2023 -0400
Fold conversion to float into V4SI vsx_extract from memory.
This patch folds conversion to floating point of vsx_extract from memory of V4SI
elements where the element number is constant. This code optimizes things so it
will load the integer with LFIWAX or LFIWZX directly into a vector register
rather than loading it into a GPR and doing a direct move operation.
2023-04-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (FL_CONSTRAINT): New mode attribute.
(SIGN_ZERO_EXTEND): New mode attribute.
(vsx_extract_v4si_load_to_<uns><mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 40 ++++++++++++++++++++++
| 38 ++++++++++++++++++++
| 26 ++++++++++++++
3 files changed, 104 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9be15b02af2..9c486a0cc79 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -251,6 +251,17 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
+;; Constraint to use for floating point types that a direct conversion
+;; from 64-bit integer to floating point.
+(define_mode_attr FL_CONSTRAINT [(SF "wa")
+ (DF "wa")
+ (KF "v")
+ (TF "v")])
+
+;; Whether to use SIGN or ZERO when depending on the floating point conversion.
+(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND")
+ (unsigned_float "ZERO_EXTEND")])
+
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -4051,6 +4062,35 @@
(set_attr "length" "4,4,12,8,12")
(set_attr "isa" "*,*,*,p9v,p9v")])
+;; Extract a V4SI element from memory with constant element number and convert
+;; it to SFmode, DFmode, KFmode, or possibly TFmode using either signed or
+;; unsigned conversion.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
+ [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONSTRAINT>,<FL_CONSTRAINT>")
+ (any_float:FL_CONV
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
+ (clobber (match_scratch:DI 3 "=&b,&b"))
+ (clobber (match_scratch:DI 4 "=f,v"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (match_dup 5))
+ (set (match_dup 0)
+ (any_float:FL_CONV (match_dup 4)))]
+{
+ if (GET_CODE (operands[4]) == SCRATCH)
+ operands[4] = gen_reg_rtx (DImode);
+
+ rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+ operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")
+ (set_attr "isa" "*,p8v")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..86077a060a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,38 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and convert the value to float, and double by loading the value
+ directly into a vector register, and not loading up the GPRs first. */
+
+#include <altivec.h>
+
+float
+extract_float_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
+}
+
+double
+extract_double_uns_v4si_3 (vector unsigned int *p)
+{
+ return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..9e46caa8277
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-require-effective-target float128_hw } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and convert the value _Float128 by loading the value directly into a
+ vector register, and not loading up the GPRs first. */
+
+#include <altivec.h>
+
+_Float128
+extract_ieee_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lxsiwzx. */
+}
+
+_Float128
+extract_ieee_uns_v4si_3 (vector unsigned int *p)
+{
+ return vec_extract (*p, 3); /* lxsiwzx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-04-20 23:46 UTC | newest]
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2023-04-19 22:18 [gcc(refs/users/meissner/heads/work119)] Fold conversion to float into V4SI vsx_extract from memory Michael Meissner
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2023-04-20 23:46 Michael Meissner
2023-04-19 22:04 Michael Meissner
2023-04-19 20:53 Michael Meissner
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