[gcc r14-97] Re-arrange sections of i386 cpuid

[gcc r14-97] Re-arrange sections of i386 cpuid

[Haochen Jiang]

https://gcc.gnu.org/g:fd7ecd8010c9967b79fa35d337d6fd27de303a72

commit r14-97-gfd7ecd8010c9967b79fa35d337d6fd27de303a72
Author: Mo, Zewei <zewei.mo@intel.com>
Date:   Tue Jan 10 16:11:02 2023 +0800

    Re-arrange sections of i386 cpuid
    
    gcc/ChangeLog:
    
            * config/i386/cpuid.h: Open a new section for Extended Features
            Leaf (%eax == 7, %ecx == 0) and Extended Features Sub-leaf (%eax == 7,
            %ecx == 1).

Diff:
---
 gcc/config/i386/cpuid.h | 61 ++++++++++++++++++++++++++-----------------------
 1 file changed, 32 insertions(+), 29 deletions(-)

diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index e1d6d2ff77c..4cc44615cf6 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -24,15 +24,6 @@
 #ifndef _CPUID_H_INCLUDED
 #define _CPUID_H_INCLUDED
 
-/* %eax */
-#define bit_RAOINT	(1 << 3)
-#define bit_AVXVNNI	(1 << 4)
-#define bit_AVX512BF16	(1 << 5)
-#define bit_CMPCCXADD	(1 << 7)
-#define bit_AMX_FP16	(1 << 21)
-#define bit_HRESET	(1 << 22)
-#define bit_AVXIFMA	(1 << 23)
-
 /* %ecx */
 #define bit_SSE3	(1 << 0)
 #define bit_PCLMUL	(1 << 1)
@@ -52,10 +43,7 @@
 #define bit_RDRND	(1 << 30)
 
 /* %edx */
-#define bit_AVXVNNIINT8 (1 << 4)
-#define bit_AVXNECONVERT (1 << 5)
 #define bit_CMPXCHG8B	(1 << 8)
-#define bit_PREFETCHI	(1 << 14)
 #define bit_CMOV	(1 << 15)
 #define bit_MMX		(1 << 23)
 #define bit_FXSAVE	(1 << 24)
@@ -84,19 +72,19 @@
 #define bit_CLZERO	(1 << 0)
 #define bit_WBNOINVD	(1 << 9)
 
-/* Extended Features (%eax == 7) */
+/* Extended Features Leaf (%eax == 7, %ecx == 0) */
 /* %ebx */
 #define bit_FSGSBASE	(1 << 0)
-#define bit_SGX (1 << 2)
-#define bit_BMI	(1 << 3)
-#define bit_HLE	(1 << 4)
+#define bit_SGX		(1 << 2)
+#define bit_BMI		(1 << 3)
+#define bit_HLE		(1 << 4)
 #define bit_AVX2	(1 << 5)
 #define bit_BMI2	(1 << 8)
-#define bit_RTM	(1 << 11)
+#define bit_RTM		(1 << 11)
 #define bit_AVX512F	(1 << 16)
 #define bit_AVX512DQ	(1 << 17)
 #define bit_RDSEED	(1 << 18)
-#define bit_ADX	(1 << 19)
+#define bit_ADX		(1 << 19)
 #define bit_AVX512IFMA	(1 << 21)
 #define bit_CLFLUSHOPT	(1 << 23)
 #define bit_CLWB	(1 << 24)
@@ -108,40 +96,55 @@
 #define bit_AVX512VL	(1u << 31)
 
 /* %ecx */
-#define bit_PREFETCHWT1	  (1 << 0)
+#define bit_PREFETCHWT1	(1 << 0)
 #define bit_AVX512VBMI	(1 << 1)
-#define bit_PKU	(1 << 3)
+#define bit_PKU		(1 << 3)
 #define bit_OSPKE	(1 << 4)
 #define bit_WAITPKG	(1 << 5)
 #define bit_AVX512VBMI2	(1 << 6)
 #define bit_SHSTK	(1 << 7)
 #define bit_GFNI	(1 << 8)
 #define bit_VAES	(1 << 9)
-#define bit_AVX512VNNI	(1 << 11)
 #define bit_VPCLMULQDQ	(1 << 10)
+#define bit_AVX512VNNI	(1 << 11)
 #define bit_AVX512BITALG	(1 << 12)
 #define bit_AVX512VPOPCNTDQ	(1 << 14)
 #define bit_RDPID	(1 << 22)
+#define bit_KL		(1 << 23)
+#define bit_CLDEMOTE	(1 << 25)
 #define bit_MOVDIRI	(1 << 27)
 #define bit_MOVDIR64B	(1 << 28)
 #define bit_ENQCMD	(1 << 29)
-#define bit_CLDEMOTE	(1 << 25)
-#define bit_KL		(1 << 23)
 
 /* %edx */
-#define bit_AVX5124VNNIW (1 << 2)
-#define bit_AVX5124FMAPS (1 << 3)
+#define bit_AVX5124VNNIW	(1 << 2)
+#define bit_AVX5124FMAPS	(1 << 3)
+#define bit_UINTR	(1 << 5)
 #define bit_AVX512VP2INTERSECT	(1 << 8)
-#define bit_AVX512FP16   (1 << 23)
-#define bit_IBT	(1 << 20)
-#define bit_UINTR (1 << 5)
-#define bit_PCONFIG	(1 << 18)
 #define bit_SERIALIZE	(1 << 14)
 #define bit_TSXLDTRK    (1 << 16)
+#define bit_PCONFIG	(1 << 18)
+#define bit_IBT         (1 << 20)
 #define bit_AMX_BF16    (1 << 22)
+#define bit_AVX512FP16	(1 << 23)
 #define bit_AMX_TILE    (1 << 24)
 #define bit_AMX_INT8    (1 << 25)
+
+/* Extended Features Sub-leaf (%eax == 7, %ecx == 1) */
+/* %eax */
+#define bit_RAOINT      (1 << 3)
+#define bit_AVXVNNI     (1 << 4)
+#define bit_AVX512BF16  (1 << 5)
+#define bit_CMPCCXADD   (1 << 7)
 #define bit_AMX_COMPLEX (1 << 8)
+#define bit_AMX_FP16    (1 << 21)
+#define bit_HRESET      (1 << 22)
+#define bit_AVXIFMA     (1 << 23)
+
+/* %edx */
+#define bit_AVXVNNIINT8 (1 << 4)
+#define bit_AVXNECONVERT	(1 << 5)
+#define bit_PREFETCHI	(1 << 14)
 
 /* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
 #define bit_XSAVEOPT	(1 << 0)