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* [gcc(refs/users/meissner/heads/work119)] Fold sign or zero convert into variable vsx_extract from memory.
@ 2023-04-21 15:39 Michael Meissner
  0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-21 15:39 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:a616f64dd3f782f8ef7a0fca48d8de7fce7a0309

commit a616f64dd3f782f8ef7a0fca48d8de7fce7a0309
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 11:39:39 2023 -0400

    Fold sign or zero convert into variable vsx_extract from memory.
    
    This patch folds sign or zero convert operations into vsx_extract from memory
    where the element number is constant.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_<mode>_var_load_to_udi): New insn.
            (vsx_extract_<mode>_var_load_to_sdi): New insn.
            (vsx_extract_v8hi_var_load_to_<su>si): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
            * gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
            * gcc.target/powerpc/vec-extract-mem-short-2.c: New file.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 69 ++++++++++++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-char-2.c    | 17 ++++++
 .../gcc.target/powerpc/vec-extract-mem-int-3.c     | 30 ++++++++++
 .../gcc.target/powerpc/vec-extract-mem-short-2.c   | 26 ++++++++
 4 files changed, 142 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d6b72a2fe33..3364a0791c2 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4145,6 +4145,75 @@
    (set_attr "length" "12,16,12,16")
    (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
 
+;; Extract a V16QI/V8HI/V4SI element from memory with a variable element number
+;; and zero extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+	(zero_extend:DI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(zero_extend:DI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], <VEC_base>mode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "12,16,12,16")
+   (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI/V4SI element from memory with a variable element number
+;; and sign extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+	(sign_extend:DI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], <VEC_base>mode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "12,16,12,16")
+   (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI element from memory with a variable element number
+;; and zero or sign extend it to SImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_<su>si"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,v,v")
+	(any_extend:SI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(any_extend:SI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], HImode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "12,16,16,20")
+   (set_attr "isa" "*,*,p9v,p9v")])
+
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"
   [(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
new file mode 100644
index 00000000000..ee6fb79993a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   QImode and fold the zero extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+unsigned long long
+extract_uns_var_v16qi (vector unsigned char *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lbzx, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..c4413fc158f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   SImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwax, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwzx, no rldicl.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M}   1 } } */
+/* { dg-final { scan-assembler-not   {\mextsw\M}    } } */
+
+/* There are 2 rldicl's to ensure the variable element number is between 0..3,
+   but there is not a third one to do the zero extension after the unsigned
+   int load.  */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..efb5447f11b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   HImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwax, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v8hi_var (vector unsigned short *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwzx, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax\M}     1 } } */
+/* { dg-final { scan-assembler-times {\mlhzx\M}     1 } } */
+/* { dg-final { scan-assembler-not   {\mextsh\M}      } } */
+/* { dg-final { scan-assembler-not   {\mrlwinm\M}     } } */

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Fold sign or zero convert into variable vsx_extract from memory.
@ 2023-04-21 15:30 Michael Meissner
  0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-21 15:30 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:0edb1ad34f8ced0f13b45d430cd90f7a1204be5a

commit 0edb1ad34f8ced0f13b45d430cd90f7a1204be5a
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 11:29:45 2023 -0400

    Fold sign or zero convert into variable vsx_extract from memory.
    
    This patch folds sign or zero convert operations into vsx_extract from memory
    where the element number is constant.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_<mode>_var_load_to_udi): New insn.
            (vsx_extract_<mode>_var_load_to_sdi): New insn.
            (vsx_extract_v8hi_var_load_to_<su>si): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
            * gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
            * gcc.target/powerpc/vec-extract-mem-short-2.c: New file.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 69 ++++++++++++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-char-2.c    | 17 ++++++
 .../gcc.target/powerpc/vec-extract-mem-int-3.c     | 26 ++++++++
 .../gcc.target/powerpc/vec-extract-mem-short-2.c   | 26 ++++++++
 4 files changed, 138 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d6b72a2fe33..3364a0791c2 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4145,6 +4145,75 @@
    (set_attr "length" "12,16,12,16")
    (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
 
+;; Extract a V16QI/V8HI/V4SI element from memory with a variable element number
+;; and zero extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+	(zero_extend:DI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(zero_extend:DI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], <VEC_base>mode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "12,16,12,16")
+   (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI/V4SI element from memory with a variable element number
+;; and sign extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+	(sign_extend:DI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], <VEC_base>mode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "12,16,12,16")
+   (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI element from memory with a variable element number
+;; and zero or sign extend it to SImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_<su>si"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,v,v")
+	(any_extend:SI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(any_extend:SI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], HImode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "12,16,16,20")
+   (set_attr "isa" "*,*,p9v,p9v")])
+
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"
   [(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
new file mode 100644
index 00000000000..ee6fb79993a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   QImode and fold the zero extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+unsigned long long
+extract_uns_var_v16qi (vector unsigned char *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lbzx, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..437001a6177
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   SImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwax, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwzx, no rldicl.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-not   {\mextsw\M}    } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..efb5447f11b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   HImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwax, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v8hi_var (vector unsigned short *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwzx, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax\M}     1 } } */
+/* { dg-final { scan-assembler-times {\mlhzx\M}     1 } } */
+/* { dg-final { scan-assembler-not   {\mextsh\M}      } } */
+/* { dg-final { scan-assembler-not   {\mrlwinm\M}     } } */

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Fold sign or zero convert into variable vsx_extract from memory.
@ 2023-04-21  4:08 Michael Meissner
  0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-21  4:08 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:8c02d3442f8703c583c3e3e4d4c23f525914ee85

commit 8c02d3442f8703c583c3e3e4d4c23f525914ee85
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 00:08:18 2023 -0400

    Fold sign or zero convert into variable vsx_extract from memory.
    
    This patch folds sign or zero convert operations into vsx_extract from memory
    where the element number is constant.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_<mode>_var_load_to_udi): New insn.
            (vsx_extract_<mode>_var_load_to_sdi): New insn.
            (vsx_extract_v8hi_var_load_to_<su>si): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
            * gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
            * gcc.target/powerpc/vec-extract-mem-short-2.c: New file.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 69 ++++++++++++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-char-2.c    | 17 ++++++
 .../gcc.target/powerpc/vec-extract-mem-int-3.c     | 26 ++++++++
 .../gcc.target/powerpc/vec-extract-mem-short-2.c   | 26 ++++++++
 4 files changed, 138 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d6b72a2fe33..3364a0791c2 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4145,6 +4145,75 @@
    (set_attr "length" "12,16,12,16")
    (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
 
+;; Extract a V16QI/V8HI/V4SI element from memory with a variable element number
+;; and zero extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+	(zero_extend:DI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(zero_extend:DI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], <VEC_base>mode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "12,16,12,16")
+   (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI/V4SI element from memory with a variable element number
+;; and sign extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+	(sign_extend:DI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], <VEC_base>mode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "12,16,12,16")
+   (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI element from memory with a variable element number
+;; and zero or sign extend it to SImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_<su>si"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,v,v")
+	(any_extend:SI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(any_extend:SI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], HImode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "12,16,16,20")
+   (set_attr "isa" "*,*,p9v,p9v")])
+
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"
   [(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
new file mode 100644
index 00000000000..ee6fb79993a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   QImode and fold the zero extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+unsigned long long
+extract_uns_var_v16qi (vector unsigned char *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lbzx, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..f89eb617770
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   SImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwax, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwzx, no rldicl.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M}   1 } } */
+/* { dg-final { scan-assembler-not   {\mextsw\M}    } } */
+/* { dg-final { scan-assembler-not   {\mrldicl\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..efb5447f11b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   HImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwax, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v8hi_var (vector unsigned short *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwzx, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax\M}     1 } } */
+/* { dg-final { scan-assembler-times {\mlhzx\M}     1 } } */
+/* { dg-final { scan-assembler-not   {\mextsh\M}      } } */
+/* { dg-final { scan-assembler-not   {\mrlwinm\M}     } } */

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Fold sign or zero convert into variable vsx_extract from memory.
@ 2023-04-21  3:43 Michael Meissner
  0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-21  3:43 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:0a839c12efa948a15d11c4882d337347d5bfaff5

commit 0a839c12efa948a15d11c4882d337347d5bfaff5
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 20 23:43:15 2023 -0400

    Fold sign or zero convert into variable vsx_extract from memory.
    
    This patch folds sign or zero convert operations into vsx_extract from memory
    where the element number is constant.
    
    2023-04-20   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_<mode>_var_load_to_udi): New insn.
            (vsx_extract_<mode>_var_load_to_sdi): New insn.
            (vsx_extract_v8hi_var_load_to_<su>si): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
            * gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
            * gcc.target/powerpc/vec-extract-mem-short-2.c: New file.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 69 ++++++++++++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-char-2.c    | 17 ++++++
 .../gcc.target/powerpc/vec-extract-mem-int-3.c     | 26 ++++++++
 .../gcc.target/powerpc/vec-extract-mem-short-2.c   | 26 ++++++++
 4 files changed, 138 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index fd17d0c29f1..778d067e533 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4142,6 +4142,75 @@
    (set_attr "length" "4,8,4,8")
    (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
 
+;; Extract a V16QI/V8HI/V4SI element from memory with a variable element number
+;; and zero extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+	(zero_extend:DI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(zero_extend:DI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], <VEC_base>mode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "4,8,4,8")
+   (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI/V4SI element from memory with a variable element number
+;; and sign extend it to DImode.
+(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+	(sign_extend:DI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], <VEC_base>mode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "4,8,8,12")
+   (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+
+;; Extract a V8HI element from memory with a variable element number
+;; and zero or sign extend it to SImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_<su>si"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,v,v")
+	(any_extend:SI
+	 (unspec:<VEC_base>
+	  [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(any_extend:SI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], HImode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "4,8,8,12")
+   (set_attr "isa" "*,*,p9v,p9v")])
+
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"
   [(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
new file mode 100644
index 00000000000..ee6fb79993a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   QImode and fold the zero extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+unsigned long long
+extract_uns_var_v16qi (vector unsigned char *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lbzx, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..f89eb617770
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   SImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwax, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwzx, no rldicl.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M}   1 } } */
+/* { dg-final { scan-assembler-not   {\mextsw\M}    } } */
+/* { dg-final { scan-assembler-not   {\mrldicl\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..efb5447f11b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   HImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwax, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v8hi_var (vector unsigned short *p, size_t n)
+{
+  return vec_extract (*p, n);		/* lwzx, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax\M}     1 } } */
+/* { dg-final { scan-assembler-times {\mlhzx\M}     1 } } */
+/* { dg-final { scan-assembler-not   {\mextsh\M}      } } */
+/* { dg-final { scan-assembler-not   {\mrlwinm\M}     } } */

^ permalink raw reply	[flat|nested] 4+ messages in thread
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