[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert with constant element.

[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert with constant element.

[Michael Meissner]

https://gcc.gnu.org/g:90d911557e5dcfc40d07be3cfda82a497e1c0135

commit 90d911557e5dcfc40d07be3cfda82a497e1c0135
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 19:20:33 2023 -0400

    Combine vec_extract of V4SF with DF convert with constant element.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.

Diff:
---
 gcc/config/rs6000/vsx.md | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..7a5daa65472 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,6 +3549,7 @@
   [(set_attr "length" "8")
    (set_attr "type" "fp")])
 
+;; V4SF extract from memory with constant element number.
 (define_insn_and_split "*vsx_extract_v4sf_load"
   [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
 	(vec_select:SF
@@ -3567,6 +3568,27 @@
    (set_attr "length" "8")
    (set_attr "isa" "*,p7v,p9v,*")])
 
+;; V4SF extract from memory with constant element number and convert to DFmode.
+(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
+  [(set (match_operand:DF 0 "register_operand" "=f,v,v")
+	(float_extend:DF
+	 (vec_select:SF
+	  (match_operand:V4SF 1 "memory_operand" "m,Z,m")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
+   (clobber (match_scratch:P 3 "=&b,&b,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode)"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")
+   (set_attr "isa" "*,p7v,p9v")])
+
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")