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* [gcc r11-10650] rs6000: correct vector sign extend builtins on Big Endian
@ 2023-04-24 3:02 HaoChen Gui
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From: HaoChen Gui @ 2023-04-24 3:02 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:af55b56c748b86a2c7e88c3c484dcb2c8602ce7a
commit r11-10650-gaf55b56c748b86a2c7e88c3c484dcb2c8602ce7a
Author: Haochen Gui <guihaoc@gcc.gnu.org>
Date: Mon Apr 24 10:56:00 2023 +0800
rs6000: correct vector sign extend builtins on Big Endian
gcc/
PR target/108812
* config/rs6000/vsx.md (vsx_sign_extend_qi_<mode>): Rename to...
(vsx_sign_extend_v16qi_<mode>): ... this.
(vsx_sign_extend_hi_<mode>): Rename to...
(vsx_sign_extend_v8hi_<mode>): ... this.
(vsx_sign_extend_si_v2di): Rename to...
(vsx_sign_extend_v4si_v2di): ... this.
(vsignextend_qi_<mode>): Remove.
(vsignextend_hi_<mode>): Remove.
(vsignextend_si_v2di): Remove.
(vsignextend_v2di_v1ti): Remove.
(*xxspltib_<mode>_split): Replace gen_vsx_sign_extend_qi_v2di with
gen_vsx_sign_extend_v16qi_v2di and gen_vsx_sign_extend_qi_v4si
with gen_vsx_sign_extend_v16qi_v4si.
* config/rs6000/rs6000.md (split for DI constant generation):
Replace gen_vsx_sign_extend_qi_si with gen_vsx_sign_extend_v16qi_si.
(split for HSDI constant generation): Replace gen_vsx_sign_extend_qi_di
with gen_vsx_sign_extend_v16qi_di and gen_vsx_sign_extend_qi_si
with gen_vsx_sign_extend_v16qi_si.
* config/rs6000/rs6000-builtin.def (__builtin_altivec_vsignextsb2d):
Set ICODE to vsx_sign_extend_v16qi_v2di.
(__builtin_altivec_vsignextsb2w): Set ICODE to
vsx_sign_extend_v16qi_v4si.
(__builtin_altivec_visgnextsh2d): Set ICODE to
vsx_sign_extend_v8hi_v2di.
(__builtin_altivec_vsignextsh2w): Set ICODE to
vsx_sign_extend_v8hi_v4si.
(__builtin_altivec_vsignextsw2d): Set ICDE to
vsx_sign_extend_si_v2di.
(__builtin_altivec_vsignext): Set ICODE to vsx_sign_extend_v2di_v1ti.
gcc/testsuite/
PR target/108812
* gcc.target/powerpc/p9-sign_extend-runnable.c: Set corresponding
expected vectors for Big Endian.
* gcc.target/powerpc/int_128bit-runnable.c: Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.def | 12 ++--
gcc/config/rs6000/rs6000.md | 6 +-
gcc/config/rs6000/vsx.md | 82 ++--------------------
.../gcc.target/powerpc/int_128bit-runnable.c | 8 +++
.../gcc.target/powerpc/p9-sign_extend-runnable.c | 25 +++++++
5 files changed, 47 insertions(+), 86 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 931ae960b9f..b0f8c708698 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -2910,11 +2910,11 @@ BU_P9_OVERLOAD_2 (CMPRB2, "byte_in_either_range")
BU_P9_OVERLOAD_2 (CMPEQB, "byte_in_set")
\f
-BU_P9V_AV_1 (VSIGNEXTSB2W, "vsignextsb2w", CONST, vsignextend_qi_v4si)
-BU_P9V_AV_1 (VSIGNEXTSH2W, "vsignextsh2w", CONST, vsignextend_hi_v4si)
-BU_P9V_AV_1 (VSIGNEXTSB2D, "vsignextsb2d", CONST, vsignextend_qi_v2di)
-BU_P9V_AV_1 (VSIGNEXTSH2D, "vsignextsh2d", CONST, vsignextend_hi_v2di)
-BU_P9V_AV_1 (VSIGNEXTSW2D, "vsignextsw2d", CONST, vsignextend_si_v2di)
+BU_P9V_AV_1 (VSIGNEXTSB2W, "vsignextsb2w", CONST, vsx_sign_extend_v16qi_v4si)
+BU_P9V_AV_1 (VSIGNEXTSH2W, "vsignextsh2w", CONST, vsx_sign_extend_v8hi_v4si)
+BU_P9V_AV_1 (VSIGNEXTSB2D, "vsignextsb2d", CONST, vsx_sign_extend_v16qi_v2di)
+BU_P9V_AV_1 (VSIGNEXTSH2D, "vsignextsh2d", CONST, vsx_sign_extend_v8hi_v2di)
+BU_P9V_AV_1 (VSIGNEXTSW2D, "vsignextsw2d", CONST, vsx_sign_extend_v4si_v2di)
/* Builtins for scalar instructions added in ISA 3.1 (power10). */
BU_P10V_AV_P (VCMPEQUT_P, "vcmpequt_p", CONST, vector_eq_v1ti_p)
@@ -2954,7 +2954,7 @@ BU_P10V_AV_2 (VNOR_V1TI, "vnor_v1ti", CONST, norv1ti3)
BU_P10V_AV_2 (VCMPNET_P, "vcmpnet_p", CONST, vector_ne_v1ti_p)
BU_P10V_AV_2 (VCMPAET_P, "vcmpaet_p", CONST, vector_ae_v1ti_p)
-BU_P10V_AV_1 (VSIGNEXTSD2Q, "vsignext", CONST, vsignextend_v2di_v1ti)
+BU_P10V_AV_1 (VSIGNEXTSD2Q, "vsignext", CONST, vsx_sign_extend_v2di_v1ti)
BU_P10V_AV_2 (VMULEUD, "vmuleud", CONST, vec_widen_umult_even_v2di)
BU_P10V_AV_2 (VMULESD, "vmulesd", CONST, vec_widen_smult_even_v2di)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4ef392ebe7b..f4ca287891a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7557,7 +7557,7 @@
rtx op0_v16qi = gen_rtx_REG (V16QImode, r);
emit_insn (gen_xxspltib_v16qi (op0_v16qi, op1));
- emit_insn (gen_vsx_sign_extend_qi_si (operands[0], op0_v16qi));
+ emit_insn (gen_vsx_sign_extend_v16qi_si (operands[0], op0_v16qi));
DONE;
})
@@ -9452,9 +9452,9 @@
emit_insn (gen_xxspltib_v16qi (op0_v16qi, op1));
if (<MODE>mode == DImode)
- emit_insn (gen_vsx_sign_extend_qi_di (operands[0], op0_v16qi));
+ emit_insn (gen_vsx_sign_extend_v16qi_di (operands[0], op0_v16qi));
else if (<MODE>mode == SImode)
- emit_insn (gen_vsx_sign_extend_qi_si (operands[0], op0_v16qi));
+ emit_insn (gen_vsx_sign_extend_v16qi_si (operands[0], op0_v16qi));
else if (<MODE>mode == HImode)
{
rtx op0_v8hi = gen_rtx_REG (V8HImode, r);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f2260badf70..bb44109c7bc 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1145,10 +1145,10 @@
emit_insn (gen_xxspltib_v16qi (tmp, GEN_INT (value)));
if (<MODE>mode == V2DImode)
- emit_insn (gen_vsx_sign_extend_qi_v2di (op0, tmp));
+ emit_insn (gen_vsx_sign_extend_v16qi_v2di (op0, tmp));
else if (<MODE>mode == V4SImode)
- emit_insn (gen_vsx_sign_extend_qi_v4si (op0, tmp));
+ emit_insn (gen_vsx_sign_extend_v16qi_v4si (op0, tmp));
else if (<MODE>mode == V8HImode)
emit_insn (gen_altivec_vupkhsb (op0, tmp));
@@ -4892,27 +4892,9 @@
"vextsd2q %0,%1"
[(set_attr "type" "vecexts")])
-(define_expand "vsignextend_v2di_v1ti"
- [(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
- (unspec:V1TI [(match_operand:V2DI 1 "vsx_register_operand" "v")]
- UNSPEC_VSX_SIGN_EXTEND))]
- "TARGET_POWER10"
-{
- if (BYTES_BIG_ENDIAN)
- {
- rtx tmp = gen_reg_rtx (V2DImode);
-
- emit_insn (gen_altivec_vrevev2di2(tmp, operands[1]));
- emit_insn (gen_vsx_sign_extend_v2di_v1ti(operands[0], tmp));
- DONE;
- }
-
- emit_insn (gen_vsx_sign_extend_v2di_v1ti(operands[0], operands[1]));
-})
-
;; ISA 3.0 vector extend sign support
-(define_insn "vsx_sign_extend_qi_<mode>"
+(define_insn "vsx_sign_extend_v16qi_<mode>"
[(set (match_operand:VSINT_84 0 "vsx_register_operand" "=v")
(unspec:VSINT_84
[(match_operand:V16QI 1 "vsx_register_operand" "v")]
@@ -4921,25 +4903,7 @@
"vextsb2<wd> %0,%1"
[(set_attr "type" "vecexts")])
-(define_expand "vsignextend_qi_<mode>"
- [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
- (unspec:VIlong
- [(match_operand:V16QI 1 "vsx_register_operand" "v")]
- UNSPEC_VSX_SIGN_EXTEND))]
- "TARGET_P9_VECTOR"
-{
- if (BYTES_BIG_ENDIAN)
- {
- rtx tmp = gen_reg_rtx (V16QImode);
- emit_insn (gen_altivec_vrevev16qi2(tmp, operands[1]));
- emit_insn (gen_vsx_sign_extend_qi_<mode>(operands[0], tmp));
- }
- else
- emit_insn (gen_vsx_sign_extend_qi_<mode>(operands[0], operands[1]));
- DONE;
-})
-
-(define_insn "vsx_sign_extend_hi_<mode>"
+(define_insn "vsx_sign_extend_v8hi_<mode>"
[(set (match_operand:VSINT_84 0 "vsx_register_operand" "=v")
(unspec:VSINT_84
[(match_operand:V8HI 1 "vsx_register_operand" "v")]
@@ -4948,25 +4912,7 @@
"vextsh2<wd> %0,%1"
[(set_attr "type" "vecexts")])
-(define_expand "vsignextend_hi_<mode>"
- [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
- (unspec:VIlong
- [(match_operand:V8HI 1 "vsx_register_operand" "v")]
- UNSPEC_VSX_SIGN_EXTEND))]
- "TARGET_P9_VECTOR"
-{
- if (BYTES_BIG_ENDIAN)
- {
- rtx tmp = gen_reg_rtx (V8HImode);
- emit_insn (gen_altivec_vrevev8hi2(tmp, operands[1]));
- emit_insn (gen_vsx_sign_extend_hi_<mode>(operands[0], tmp));
- }
- else
- emit_insn (gen_vsx_sign_extend_hi_<mode>(operands[0], operands[1]));
- DONE;
-})
-
-(define_insn "vsx_sign_extend_si_v2di"
+(define_insn "vsx_sign_extend_v4si_v2di"
[(set (match_operand:V2DI 0 "vsx_register_operand" "=v")
(unspec:V2DI [(match_operand:V4SI 1 "vsx_register_operand" "v")]
UNSPEC_VSX_SIGN_EXTEND))]
@@ -4974,24 +4920,6 @@
"vextsw2d %0,%1"
[(set_attr "type" "vecexts")])
-(define_expand "vsignextend_si_v2di"
- [(set (match_operand:V2DI 0 "vsx_register_operand" "=v")
- (unspec:V2DI [(match_operand:V4SI 1 "vsx_register_operand" "v")]
- UNSPEC_VSX_SIGN_EXTEND))]
- "TARGET_P9_VECTOR"
-{
- if (BYTES_BIG_ENDIAN)
- {
- rtx tmp = gen_reg_rtx (V4SImode);
-
- emit_insn (gen_altivec_vrevev4si2(tmp, operands[1]));
- emit_insn (gen_vsx_sign_extend_si_v2di(operands[0], tmp));
- }
- else
- emit_insn (gen_vsx_sign_extend_si_v2di(operands[0], operands[1]));
- DONE;
-})
-
;; ISA 3.1 vector sign extend
;; Move DI value from GPR to TI mode in VSX register, word 1.
(define_insn "mtvsrdd_diti_w1"
diff --git a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c
index 41e46d41401..9d216799a0f 100644
--- a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c
@@ -90,7 +90,11 @@ int main ()
vec_arg1_di[0] = 1000;
vec_arg1_di[1] = -123456;
+#ifdef __BIG_ENDIAN__
+ expected_result = -123456;
+#else
expected_result = 1000;
+#endif
vec_result = vec_signextq (vec_arg1_di);
@@ -109,7 +113,11 @@ int main ()
vec_arg1_di[0] = -123456;
vec_arg1_di[1] = 1000;
+#ifdef __BIG_ENDIAN__
+ expected_result = 1000;
+#else
expected_result = -123456;
+#endif
vec_result = vec_signextq (vec_arg1_di);
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-sign_extend-runnable.c b/gcc/testsuite/gcc.target/powerpc/p9-sign_extend-runnable.c
index fdcad019b96..03c0f1201e4 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-sign_extend-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-sign_extend-runnable.c
@@ -34,7 +34,12 @@ int main ()
/* test sign extend byte to word */
vec_arg_qi = (vector signed char) {1, 2, 3, 4, 5, 6, 7, 8,
-1, -2, -3, -4, -5, -6, -7, -8};
+
+#ifdef __BIG_ENDIAN__
+ vec_expected_wi = (vector signed int) {4, 8, -4, -8};
+#else
vec_expected_wi = (vector signed int) {1, 5, -1, -5};
+#endif
vec_result_wi = vec_signexti (vec_arg_qi);
@@ -54,7 +59,12 @@ int main ()
/* test sign extend byte to double */
vec_arg_qi = (vector signed char){1, 2, 3, 4, 5, 6, 7, 8,
-1, -2, -3, -4, -5, -6, -7, -8};
+
+#ifdef __BIG_ENDIAN__
+ vec_expected_di = (vector signed long long int){8, -8};
+#else
vec_expected_di = (vector signed long long int){1, -1};
+#endif
vec_result_di = vec_signextll(vec_arg_qi);
@@ -72,7 +82,12 @@ int main ()
/* test sign extend short to word */
vec_arg_hi = (vector signed short int){1, 2, 3, 4, -1, -2, -3, -4};
+
+#ifdef __BIG_ENDIAN__
+ vec_expected_wi = (vector signed int){2, 4, -2, -4};
+#else
vec_expected_wi = (vector signed int){1, 3, -1, -3};
+#endif
vec_result_wi = vec_signexti(vec_arg_hi);
@@ -90,7 +105,12 @@ int main ()
/* test sign extend short to double word */
vec_arg_hi = (vector signed short int ){1, 3, 5, 7, -1, -3, -5, -7};
+
+#ifdef __BIG_ENDIAN__
+ vec_expected_di = (vector signed long long int){7, -7};
+#else
vec_expected_di = (vector signed long long int){1, -1};
+#endif
vec_result_di = vec_signextll(vec_arg_hi);
@@ -108,7 +128,12 @@ int main ()
/* test sign extend word to double word */
vec_arg_wi = (vector signed int ){1, 3, -1, -3};
+
+#ifdef __BIG_ENDIAN__
+ vec_expected_di = (vector signed long long int){3, -3};
+#else
vec_expected_di = (vector signed long long int){1, -1};
+#endif
vec_result_di = vec_signextll(vec_arg_wi);
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