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* [gcc r14-191] [3/4] aarch64: Convert UABAL and SABAL patterns to standard RTL codes
@ 2023-04-24 8:48 Kyrylo Tkachov
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From: Kyrylo Tkachov @ 2023-04-24 8:48 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e0472ed5aeeb908cb34be57a74c520c90bcb79d8
commit r14-191-ge0472ed5aeeb908cb34be57a74c520c90bcb79d8
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Mon Apr 24 09:43:55 2023 +0100
[3/4] aarch64: Convert UABAL and SABAL patterns to standard RTL codes
With the SABDL and UABDL patterns converted, the accumulating forms of them UABAL and SABAL are not much more complicated.
There's an accumulator argument that we, err, accumulate into with a PLUS once all the widening is done.
Some necessary renaming of patterns relating to the removal of UNSPEC_SABAL and UNSPEC_UABAL is included.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_<sur>abal<mode>): Rename to...
(aarch64_<su>abal<mode>): ... This. Use RTL codes instead of unspec.
(<sur>sadv16qi): Rename to...
(<su>sadv16qi): ... This. Adjust for the above.
* config/aarch64/aarch64-sve.md (<sur>sad<vsi2qi>): Rename to...
(<su>sad<vsi2qi>): ... This. Adjust for the above.
* config/aarch64/aarch64.md (UNSPEC_SABAL, UNSPEC_UABAL): Delete.
* config/aarch64/iterators.md (ABAL): Delete.
(sur): Remove handling of UNSPEC_SABAL and UNSPEC_UABAL.
Diff:
---
gcc/config/aarch64/aarch64-simd.md | 38 ++++++++++++++++++++++----------------
gcc/config/aarch64/aarch64-sve.md | 8 ++++----
gcc/config/aarch64/aarch64.md | 2 --
gcc/config/aarch64/iterators.md | 4 ----
4 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 6c628681a6d..51bb6cf357c 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -952,14 +952,20 @@
}
)
-(define_insn "aarch64_<sur>abal<mode>"
+(define_insn "aarch64_<su>abal<mode>"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
- (unspec:<VWIDE> [(match_operand:VD_BHSI 2 "register_operand" "w")
- (match_operand:VD_BHSI 3 "register_operand" "w")
- (match_operand:<VWIDE> 1 "register_operand" "0")]
- ABAL))]
+ (plus:<VWIDE>
+ (zero_extend:<VWIDE>
+ (minus:VD_BHSI
+ (USMAX:VD_BHSI
+ (match_operand:VD_BHSI 2 "register_operand" "w")
+ (match_operand:VD_BHSI 3 "register_operand" "w"))
+ (<max_opp>:VD_BHSI
+ (match_dup 2)
+ (match_dup 3))))
+ (match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- "<sur>abal\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>"
+ "<su>abal\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "type" "neon_arith_acc<q>")]
)
@@ -1004,10 +1010,10 @@
;; but for TARGET_DOTPROD still emits a UDOT as the absolute difference is
;; unsigned.
-(define_expand "<sur>sadv16qi"
+(define_expand "<su>sadv16qi"
[(use (match_operand:V4SI 0 "register_operand"))
- (unspec:V16QI [(use (match_operand:V16QI 1 "register_operand"))
- (use (match_operand:V16QI 2 "register_operand"))] ABAL)
+ (USMAX:V16QI (match_operand:V16QI 1 "register_operand")
+ (match_operand:V16QI 2 "register_operand"))
(use (match_operand:V4SI 3 "register_operand"))]
"TARGET_SIMD"
{
@@ -1015,18 +1021,18 @@
{
rtx ones = force_reg (V16QImode, CONST1_RTX (V16QImode));
rtx abd = gen_reg_rtx (V16QImode);
- emit_insn (gen_aarch64_<sur>abdv16qi (abd, operands[1], operands[2]));
+ emit_insn (gen_aarch64_<su>abdv16qi (abd, operands[1], operands[2]));
emit_insn (gen_udot_prodv16qi (operands[0], abd, ones, operands[3]));
DONE;
}
rtx reduc = gen_reg_rtx (V8HImode);
- emit_insn (gen_aarch64_<sur>abdl2v16qi (reduc, operands[1],
+ emit_insn (gen_aarch64_<su>abdl2v16qi (reduc, operands[1],
operands[2]));
- emit_insn (gen_aarch64_<sur>abalv8qi (reduc, reduc,
- gen_lowpart (V8QImode, operands[1]),
- gen_lowpart (V8QImode,
- operands[2])));
- emit_insn (gen_aarch64_<sur>adalpv8hi (operands[3], operands[3], reduc));
+ emit_insn (gen_aarch64_<su>abalv8qi (reduc, reduc,
+ gen_lowpart (V8QImode, operands[1]),
+ gen_lowpart (V8QImode,
+ operands[2])));
+ emit_insn (gen_aarch64_<su>adalpv8hi (operands[3], operands[3], reduc));
emit_move_insn (operands[0], operands[3]);
DONE;
}
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 7533b956686..b11b55f7ac7 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -6955,16 +6955,16 @@
;; [SU]ABD diff.b, p0/m, op1.b, op2.b
;; MOVPRFX op0, op3 // If necessary
;; UDOT op0.s, diff.b, ones.b
-(define_expand "<sur>sad<vsi2qi>"
+(define_expand "<su>sad<vsi2qi>"
[(use (match_operand:SVE_FULL_SDI 0 "register_operand"))
- (unspec:<VSI2QI> [(use (match_operand:<VSI2QI> 1 "register_operand"))
- (use (match_operand:<VSI2QI> 2 "register_operand"))] ABAL)
+ (USMAX:<VSI2QI> (match_operand:<VSI2QI> 1 "register_operand")
+ (match_operand:<VSI2QI> 2 "register_operand"))
(use (match_operand:SVE_FULL_SDI 3 "register_operand"))]
"TARGET_SVE"
{
rtx ones = force_reg (<VSI2QI>mode, CONST1_RTX (<VSI2QI>mode));
rtx diff = gen_reg_rtx (<VSI2QI>mode);
- emit_insn (gen_<sur>abd<vsi2qi>_3 (diff, operands[1], operands[2]));
+ emit_insn (gen_<su>abd<vsi2qi>_3 (diff, operands[1], operands[2]));
emit_insn (gen_udot_prod<vsi2qi> (operands[0], diff, ones, operands[3]));
DONE;
}
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 1b2bdf5c550..426eb85d2db 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -204,7 +204,6 @@
UNSPEC_PRLG_STK
UNSPEC_REV
UNSPEC_RBIT
- UNSPEC_SABAL
UNSPEC_SABAL2
UNSPEC_SADALP
UNSPEC_SCVTF
@@ -226,7 +225,6 @@
UNSPEC_TLSLE24
UNSPEC_TLSLE32
UNSPEC_TLSLE48
- UNSPEC_UABAL
UNSPEC_UABAL2
UNSPEC_UADALP
UNSPEC_UCVTF
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index bd4415d6008..0195cdc545e 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2567,9 +2567,6 @@
;; Int Iterators.
;; -------------------------------------------------------------------
-;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
-(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
-
;; The unspec codes for the SABAL2, UABAL2 AdvancedSIMD instructions.
(define_int_iterator ABAL2 [UNSPEC_SABAL2 UNSPEC_UABAL2])
@@ -3354,7 +3351,6 @@
(UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
(UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
(UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
- (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
(UNSPEC_SABAL2 "s") (UNSPEC_UABAL2 "u")
(UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
(UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
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