[gcc/marxin/heads/gcov-json-add-calls] (88 commits) Refactor how are blocks, lines and branches printed.

[gcc/marxin/heads/gcov-json-add-calls] (88 commits) Refactor how are blocks, lines and branches printed.

[Martin Liska]

The branch 'marxin/heads/gcov-json-add-calls' was updated to point to:

 69685de0593... Refactor how are blocks, lines and branches printed.

It previously pointed to:

 0dc190d16fb... gcov: add info about "calls" to JSON output format

Diff:

!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
-------------------------------------------------------------------

  0dc190d... gcov: add info about "calls" to JSON output format


Summary of changes (added commits):
-----------------------------------

  69685de... Refactor how are blocks, lines and branches printed.
  f7faa9d... gcov: add info about "calls" to JSON output format
  2abc7b6... MAINTAINERS: fix sorting of names (*)
  c729a17... doc: Update install.texi for GCC 13 (*)
  9fd4a38... aarch64: PR target/109406 Add support for SVE2 unpredicated (*)
  636e227... [4/4] aarch64: Convert UABAL2 and SABAL2 patterns to standa (*)
  e0472ed... [3/4] aarch64: Convert UABAL and SABAL patterns to standard (*)
  6c82641... [2/4] aarch64: Convert UABDL2 and SABDL2 patterns to standa (*)
  c606549... [1/4] aarch64: Convert UABDL and SABDL patterns to standard (*)
  6ec565d... aarch64: Add pattern to match zero-extending scalar result  (*)
  60bf26a... This replaces uses of last_stmt where we do not require deb (*)
  28c06d0... Avoid repeated forwarder_block_p calls in CFG cleanup (*)
  ff8f954... RISC-V: Eliminate redundant vsetvli for duplicate AVL def (*)
  c5a1fa5... RISC-V: Add function comment for cleanup_insns. (*)
  4eae76d... RISC-V: Optimize fault only first load (*)
  8311c26... Add testcases for ffs/ctz vectorization. (*)
  6c06b9e... Daily bump. (*)
  8d7223f... modula2: Add -lnsl -lsocket libraries to gcc/testsuite/lib/ (*)
  7e26fd6... aarch64: Annotate fcvtn pattern for vec_concat with zeroes (*)
  3b13c59... aarch64: Add vect_concat with zeroes annotation to addp pat (*)
  8ffff5e... [xstormy16] Update xstormy16_rtx_costs. (*)
  9a6e5b9... [xstormy16] Add extendhisi2 and zero_extendhisi2 patterns t (*)
  987caaa... [xstormy16] Improved SImode shifts by two bits. (*)
  5830953... Handle NANs in frange::operator== [PR109593] (*)
  525713e... Adjust testcases after better RA decision. (*)
  0368d16... Use NO_REGS in cost calculation when the preferred register (*)
  6ab856a... Daily bump. (*)
  e81b29a... PHIOPT: Improve readability of tree_ssa_phiopt_worker (*)
  84325f1... PHIOPT: Improve minmax diamond detection for phiopt1 (*)
  911db25... [Committed] Move new test case to gcc.target/avr/mmcu/pr548 (*)
  eb385a4... Fortran: function results never have the ALLOCATABLE attrib (*)
  7a0cbaf... testsuite: Fix up pr109011-*.c tests for powerpc [PR109572] (*)
  195270d... Fix up bootstrap with GCC 4.[89] after RAII auto_mpfr and a (*)
  00c4986... Adjust rx movsicc tests (*)
  c58c077... match.pd: Fix fneg/fadd optimization [PR109583] (*)
  cda246f... Update loop estimate after header duplication (*)
  6d7f9eb... Daily bump. (*)
  f828503... Do not fold ADDR_EXPR conditions leading to builtin_unreach (*)
  03cebd3... c++: fix 'unsigned typedef-name' extension [PR108099] (*)
  7d115e0... configure: Only create serdep.tmp if needed (*)
  79c7312... gcc/m2: Drop references to $(P) (*)
  f1f1819... Adjust x86 testsuite for recent if-conversion cost checking (*)
  8819514... aarch64: Emit single-instruction for smin (x, 0) and smax ( (*)
  573624e... PR target/108779 aarch64: Implement -mtp= option (*)
  f824216... aarch64: PR target/99195 Add scheme to optimise away vec_co (*)
  857c8e3... c++, tree: optimize walk_tree_1 and cp_walk_subtrees (*)
  7508aac... 	Add Ajit Kumar Agarwal to write after approval (*)
  f7b9258... Fix boostrap failure in tree-ssa-loop-ch.cc (*)
  1fe9bef... expansion: make layout of x_shift*cost[][][] more efficient (*)
  e6f689d... MAINTAINERS: add Vineet Gupta to write after approval (*)
  e306501... [aarch64] Use force_reg instead of copy_to_mode_reg. (*)
  18c9427... i386: Remove REG_OK_FOR_INDEX/REG_OK_FOR_BASE and their der (*)
  2f4e451... Fix latent bug in loop header copying which forgets to upda (*)
  2e047c0... Add safe_is_a (*)
  c39cdd9... Add operator* to gimple_stmt_iterator and gphi_iterator (*)
  68c0df8... Stabilize inliner (*)
  b5c3abc... Cleanup odr_types_equivalent_p (*)
  a7e1ee3... PR modula2/109586 cc1gm2 ICE when compiling large source fi (*)
  cddfe6b... tree-optimization/109573 - avoid ICEing on unexpected live  (*)
  53dddbf... Use correct CFG orders for DF worklist processing (*)
  773cc92... change inverted_post_order_compute to inverted_rev_post_ord (*)
  94a04c2... change DF to use the proper CFG order for DF_FORWARD proble (*)
  d06e926... RISC-V: Defer vsetvli insertion to later if possible [PR108 (*)
  98d66b2... riscv: Fix <bitmanip_insn> fallout. (*)
  6afa7d3... rs6000: xfail float128 comparison test case that fails on p (*)
  4dca602... testsuite: make ppc_cpu_supports_hw as effective target key (*)
  a322f37... Fix LCM dataflow CFG order (*)
  a80c68a... LoongArch: Fix MUSL_DYNAMIC_LINKER (*)
  d51f245... RISC-V: Add local user vsetvl instruction elimination [PR10 (*)
  ce4e4f3... Daily bump. (*)
  fa3a566... update_web_docs_git: Allow setting TEXI2*, add git build de (*)
  afc7e20... c++: simplify TEMPLATE_TYPE_PARM level lowering (*)
  76fa66e... c++: use TREE_VEC for trailing args of variadic built-in tr (*)
  d180a55... c++: make strip_typedefs generalize strip_typedefs_expr (*)
  d4e8523... doc: Remove repeated word (typo) (*)
  17aa9dd... Do not ignore UNDEFINED ranges when determining PHI equival (*)
  87c9bae... tree-vect-patterns: One small vect_recog_ctz_ffs_pattern tw (*)
  3d7ab53... c: Avoid -Wenum-int-mismatch warning for redeclaration of b (*)
  1d2aa9a... [LRA]: Exclude some hard regs for multi-reg inout reload ps (*)
  cae48a9... arch: Use VIRTUAL_REGISTER_P predicate. (*)
  272484d... i386: Handle sign-extract for QImode operations with high r (*)
  07e2576... [PR target/108248] [RISC-V] Break down some bitmanip insn t (*)
  7b206ae... RISC-V: Fix RVV register order (*)
  9fde76a... RISC-V: Fix riscv/arch-19.c with different ISA spec version (*)
  a2d12ab... RISC-V: Fix wrong check of register occurrences [PR109535] (*)
  98ebdda... RISC-V: Fix simplify_ior_optimization.c on rv32 (*)
  0be4fbe... amdgcn: bug fix ldexp insn (*)
  09751f5... amdgcn: update target-supports.exp (*)

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