[gcc r14-235] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal

[gcc r14-235] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal

[Kito Cheng]

https://gcc.gnu.org/g:a8d5e14f524283484c2a466353f92f7eaadae9f7

commit r14-235-ga8d5e14f524283484c2a466353f92f7eaadae9f7
Author: Pan Li <pan2.li@intel.com>
Date:   Tue Apr 25 22:29:04 2023 +0800

    RISC-V: Bugfix for RVV vbool*_t vn_reference_equal
    
    In most architecture the precision_size of vbool*_t types are caculated
    like as the multiple of the type size.  For example:
    precision_size = type_size * 8 (aka, bit count per bytes).
    
    Unfortunately, some architecture like RISC-V will adjust the
    precision_size
    for the vbool*_t in order to align the ISA. For example as below.
    type_size      = [1, 1, 1, 1,  2,  4,  8]
    precision_size = [1, 2, 4, 8, 16, 32, 64]
    
    Then the precision_size of RISC-V vbool*_t will not be the multiple of
    the
    type_size. This PATCH try to enrich this case when comparing the
    vn_reference.
    
    Given we have the below code:
    void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict
    out) {
        vbool8_t v1 = *(vbool8_t*)in;
        vbool16_t v2 = *(vbool16_t*)in;
    
        *(vbool8_t*)(out + 100) = v1;
        *(vbool16_t*)(out + 200) = v2;
    }
    
    Before this PATCH:
    csrr    t0,vlenb
    slli    t1,t0,1
    csrr    a3,vlenb
    sub     sp,sp,t1
    slli    a4,a3,1
    add     a4,a4,sp
    addi    a2,a1,100
    vsetvli a5,zero,e8,m1,ta,ma
    sub     a3,a4,a3
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a2)
    vsm.v   v24,0(a3)
    addi    a1,a1,200
    csrr    t0,vlenb
    vsetvli a4,zero,e8,mf2,ta,ma
    slli    t1,t0,1
    vlm.v   v24,0(a3)
    vsm.v   v24,0(a1)
    add     sp,sp,t1
    jr      ra
    
    After this PATCH:
    addi    a3,a1,100
    vsetvli a4,zero,e8,m1,ta,ma
    addi    a1,a1,200
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a3)
    vsetvli a5,zero,e8,mf2,ta,ma
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a1)
    ret
    
            PR target/109272
    
    gcc/ChangeLog:
    
            * tree-ssa-sccvn.cc (vn_reference_eq): add type vector subparts
            check for vn_reference equal.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/pr108185-4.c: Update test check
            condition.
            * gcc.target/riscv/rvv/base/pr108185-5.c: Likewise.
            * gcc.target/riscv/rvv/base/pr108185-6.c: Likewise.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c |  2 +-
 gcc/tree-ssa-sccvn.cc                                | 20 ++++++++++++++++++++
 4 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
index 6e4d1cb1e44..321cd5c818e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
@@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
 /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
index 9fc659d2402..575a7842cdf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
@@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
 /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
index 98275e5267d..95a11d37016 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
@@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
 /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
index 94b793e1caf..94d6163e6ae 100644
--- a/gcc/tree-ssa-sccvn.cc
+++ b/gcc/tree-ssa-sccvn.cc
@@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
 	   && (TYPE_PRECISION (vr2->type)
 	       != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
     return false;
+  else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
+	   && VECTOR_BOOLEAN_TYPE_P (vr2->type))
+    {
+      /* Vector boolean types can have padding, verify we are dealing with
+	 the same number of elements, aka the precision of the types.
+	 For example, In most architecture the precision_size of vbool*_t
+	 types are caculated like below:
+	 precision_size = type_size * 8
+
+	 Unfortunately, the RISC-V will adjust the precision_size for the
+	 vbool*_t in order to align the ISA as below:
+	 type_size      = [1, 1, 1, 1,  2,  4,  8]
+	 precision_size = [1, 2, 4, 8, 16, 32, 64]
+
+	 Then the precision_size of RISC-V vbool*_t will not be the multiple
+	 of the type_size.  We take care of this case consolidated here.  */
+      if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
+		    TYPE_VECTOR_SUBPARTS (vr2->type)))
+	return false;
+    }
 
   i = 0;
   j = 0;