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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers. Date: Thu, 27 Apr 2023 02:57:05 +0000 (GMT) [thread overview] Message-ID: <20230427025705.23E5B3858D20@sourceware.org> (raw) https://gcc.gnu.org/g:67b9b179a830ee4a8708d2f7bdc50e5891adbc3e commit 67b9b179a830ee4a8708d2f7bdc50e5891adbc3e Author: Michael Meissner <meissner@linux.ibm.com> Date: Wed Apr 26 22:56:49 2023 -0400 Allow variable element vec_extract to be loaded into vector registers. This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a variable element number to be loaded into vector registers directly. It also will be split before register allocation. 2023-04-26 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector registers to be loaded. Split before register allocation. Diff: --- gcc/config/rs6000/vsx.md | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 003bd534119..19a502b99a3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4087,23 +4087,28 @@ } [(set_attr "isa" "p9v,*")]) -;; Variable V16QI/V8HI/V4SI extract from memory +;; Variable V16QI/V8HI/V4SI extract from memory. We need to split after reload +;; on power8 due to the vector byte swap support which creates Altivec +;; addresses. These are eliminated after register allocation since we use 'Q' +;; or 'Z' constraints. (define_insn_and_split "*vsx_extract_<mode>_var_load" - [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r") + [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>") (unspec:<VEC_base> - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b"))] + (clobber (match_scratch:DI 3 "=&b,&b"))] "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], <VEC_base>mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + <VEC_base>mode); } - [(set_attr "type" "load")]) + [(set_attr "type" "load,fpload") + (set_attr "isa" "*,<VSX_EX_ISA>")]) ;; ISA 3.1 extract (define_expand "vextractl<mode>"
next reply other threads:[~2023-04-27 2:57 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-27 2:57 Michael Meissner [this message] -- strict thread matches above, loose matches on Subject: below -- 2023-04-29 3:31 Michael Meissner 2023-04-28 18:30 Michael Meissner 2023-04-28 18:25 Michael Meissner 2023-04-28 3:28 Michael Meissner 2023-04-26 15:45 Michael Meissner 2023-04-25 15:55 Michael Meissner 2023-04-25 6:30 Michael Meissner 2023-04-25 2:18 Michael Meissner 2023-04-25 2:11 Michael Meissner
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