[gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:7f5887b68e9018ce346823aa06560ba99992a88e

commit 7f5887b68e9018ce346823aa06560ba99992a88e
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 24 22:11:21 2023 -0400

    Allow variable element vec_extract to be loaded into vector registers.
    
    This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
    variable element number to be loaded into vector registers directly.  It also
    will be split before register allocation.
    
    2023-04-24   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            (vsx_extract_<mode>_var_load): Allow vector registers to be loaded.

Diff:
---
 gcc/config/rs6000/vsx.md | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 003bd534119..cc3bc83ff9b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4089,21 +4089,22 @@
 
 ;; Variable V16QI/V8HI/V4SI extract from memory
 (define_insn_and_split "*vsx_extract_<mode>_var_load"
-  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
 	(unspec:<VEC_base>
-	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
-	  (match_operand:DI 2 "gpc_reg_operand" "r")]
+	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+	  (match_operand:DI 2 "gpc_reg_operand" "r,r")]
 	 UNSPEC_VSX_EXTRACT))
-   (clobber (match_scratch:DI 3 "=&b"))]
+   (clobber (match_scratch:DI 3 "=&b,&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
-					   operands[3], <VEC_base>mode);
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+					   operands[2], operands[3],
+					   <VEC_base>mode);
 }
-  [(set_attr "type" "load")])
+  [(set_attr "type" "load,fpload")])
 
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"