public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/meissner/heads/work119)] Allow vec_extract from memory support functions before reload
@ 2023-04-27 19:32 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-27 19:32 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b2f2c793eb6bf3619d40a876efa97be6c005d291
commit b2f2c793eb6bf3619d40a876efa97be6c005d291
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 27 15:31:34 2023 -0400
Allow vec_extract from memory support functions before reload
In the succeeding patches, I will be modifying the various vec_extract insns to
allow the split to occur before register allocation. This patch goes through
the support function rs6000_adjust_vec_address and the functions it calls to
allow them to be called before register allocation. The places that take a
scratch register will allocate a new pseudo register if they are passed a
SCRATCH register.
2023-04-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (get_vector_offset): Allow function to be
called before register allocation.
(adjust_vec_address_pcrel): Likewise.
(rs6000_adjust_vec_address): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 56 +++++++++++++++++++++++++++++++--------------
1 file changed, 39 insertions(+), 17 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3be5860dd9b..65295dbaf81 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,9 +7686,13 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- /* All insns should use the 'Q' constraint (address is a single register) if
- the element number is not a constant. */
- gcc_assert (satisfies_constraint_Q (mem));
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
+ /* After register allocation, all insns should use the 'Q' constraint
+ (address is a single register) if the element number is not a
+ constant. */
+ gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7704,6 +7708,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
+ if (can_create_pseudo_p ())
+ base_tmp = gen_reg_rtx (Pmode);
+
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7747,6 +7754,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7769,9 +7779,8 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- This function is expected to be called after reload is completed when we are
- splitting insns. The temporary BASE_TMP might be set multiple times with
- this code. */
+ The temporary BASE_TMP might be set multiple times with this code if this is
+ called after register allocation. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7784,8 +7793,11 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
+ if (GET_CODE (base_tmp) != SCRATCH)
+ {
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
+ }
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7841,6 +7853,9 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7848,26 +7863,33 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If the address isn't valid, move the address into the temporary base
- register. Some reasons it could not be valid include:
+ /* If register allocation has been done and the address isn't valid, move
+ the address into the temporary base register. Some reasons it could not
+ be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
-
- if (iform == INSN_FORM_BAD)
+ if (!can_create_pseudo_p ())
{
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
+
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
+ }
}
return change_address (mem, scalar_mode, new_addr);
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow vec_extract from memory support functions before reload
@ 2023-04-28 4:15 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-28 4:15 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:85c70ced62f93e0607f7db173b4c64ac50358f72
commit 85c70ced62f93e0607f7db173b4c64ac50358f72
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 00:14:42 2023 -0400
Allow vec_extract from memory support functions before reload
In the succeeding patches, I will be modifying the various vec_extract insns to
allow the split to occur before register allocation. This patch goes through
the support function rs6000_adjust_vec_address and the functions it calls to
allow them to be called before register allocation. The places that take a
scratch register will allocate a new pseudo register if they are passed a
SCRATCH register.
2023-04-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (get_vector_offset): Allow function to be
called before register allocation.
(adjust_vec_address_pcrel): Likewise.
(rs6000_adjust_vec_address): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 87 +++++++++++++++++++++++++++++++++++----------
1 file changed, 69 insertions(+), 18 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3be5860dd9b..0e04f7151f1 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,9 +7686,13 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- /* All insns should use the 'Q' constraint (address is a single register) if
- the element number is not a constant. */
- gcc_assert (satisfies_constraint_Q (mem));
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
+ /* After register allocation, all insns should use the 'Q' constraint
+ (address is a single register) if the element number is not a
+ constant. */
+ gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7704,6 +7708,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
+ if (can_create_pseudo_p ())
+ base_tmp = gen_reg_rtx (Pmode);
+
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7747,6 +7754,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7769,9 +7779,8 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- This function is expected to be called after reload is completed when we are
- splitting insns. The temporary BASE_TMP might be set multiple times with
- this code. */
+ The temporary BASE_TMP might be set multiple times with this code if this is
+ called after register allocation. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7784,8 +7793,11 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
+ if (GET_CODE (base_tmp) != SCRATCH)
+ {
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
+ }
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7841,33 +7853,72 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
}
+ /* Deal with Altivec style addresses. These come up on the power8 when GCC
+ generates the Altivec load/store (LVX and STVX) to eliminate byte swapping
+ the vectors. */
+ else if (GET_CODE (addr) == AND
+ && CONST_INT_P (XEXP (addr, 1))
+ && INTVAL (XEXP (addr, 1)) == -16)
+ {
+ rtx op0 = XEXP (addr, 0);
+ rtx op1 = XEXP (addr, 1);
+
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
+ /* Is this reg+reg? */
+ if (GET_CODE (op0) == PLUS)
+ {
+ rtx plus_tmp = (can_create_pseudo_p ()
+ ? gen_reg_rtx (Pmode)
+ : base_tmp);
+
+ emit_insn (gen_rtx_SET (plus_tmp, op0));
+ op0 = plus_tmp;
+ }
+
+ emit_insn (gen_rtx_SET (base_tmp,
+ gen_rtx_AND (Pmode, op0, op1)));
+ new_addr = base_tmp;
+ }
+
else
{
- emit_move_insn (base_tmp, addr);
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
+ emit_insn (gen_rtx_SET (base_tmp, addr));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If the address isn't valid, move the address into the temporary base
- register. Some reasons it could not be valid include:
+ /* If register allocation has been done and the address isn't valid, move
+ the address into the temporary base register. Some reasons it could not
+ be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
-
- if (iform == INSN_FORM_BAD)
+ if (!can_create_pseudo_p ())
{
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
+
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
+ }
}
return change_address (mem, scalar_mode, new_addr);
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow vec_extract from memory support functions before reload
@ 2023-04-27 19:44 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-27 19:44 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:311c7c391998857fff99eee8d5a4edd05607c649
commit 311c7c391998857fff99eee8d5a4edd05607c649
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 27 15:43:49 2023 -0400
Allow vec_extract from memory support functions before reload
In the succeeding patches, I will be modifying the various vec_extract insns to
allow the split to occur before register allocation. This patch goes through
the support function rs6000_adjust_vec_address and the functions it calls to
allow them to be called before register allocation. The places that take a
scratch register will allocate a new pseudo register if they are passed a
SCRATCH register.
2023-04-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (get_vector_offset): Allow function to be
called before register allocation.
(adjust_vec_address_pcrel): Likewise.
(rs6000_adjust_vec_address): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 58 +++++++++++++++++++++++++++++++--------------
1 file changed, 40 insertions(+), 18 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3be5860dd9b..332cb862f54 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,9 +7686,13 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- /* All insns should use the 'Q' constraint (address is a single register) if
- the element number is not a constant. */
- gcc_assert (satisfies_constraint_Q (mem));
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
+ /* After register allocation, all insns should use the 'Q' constraint
+ (address is a single register) if the element number is not a
+ constant. */
+ gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7704,6 +7708,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
+ if (can_create_pseudo_p ())
+ base_tmp = gen_reg_rtx (Pmode);
+
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7747,6 +7754,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7769,9 +7779,8 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- This function is expected to be called after reload is completed when we are
- splitting insns. The temporary BASE_TMP might be set multiple times with
- this code. */
+ The temporary BASE_TMP might be set multiple times with this code if this is
+ called after register allocation. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7784,8 +7793,11 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
+ if (GET_CODE (base_tmp) != SCRATCH)
+ {
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
+ }
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7841,6 +7853,9 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7848,26 +7863,33 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- emit_move_insn (base_tmp, addr);
+ if (GET_CODE (base_tmp) == SCRATCH)
+ base_tmp = gen_reg_rtx (Pmode);
+
+ emit_insn (gen_rtx_SET (base_tmp, addr));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If the address isn't valid, move the address into the temporary base
- register. Some reasons it could not be valid include:
+ /* If register allocation has been done and the address isn't valid, move
+ the address into the temporary base register. Some reasons it could not
+ be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
-
- if (iform == INSN_FORM_BAD)
+ if (!can_create_pseudo_p ())
{
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
+
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
+ }
}
return change_address (mem, scalar_mode, new_addr);
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-04-28 4:15 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-27 19:32 [gcc(refs/users/meissner/heads/work119)] Allow vec_extract from memory support functions before reload Michael Meissner
2023-04-27 19:44 Michael Meissner
2023-04-28 4:15 Michael Meissner
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).