[gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:371e826e204a8063d66b8ee92d4fcbe4499f5366

commit 371e826e204a8063d66b8ee92d4fcbe4499f5366
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 28 20:47:17 2023 -0400

    Allow consant element vec_extract to be zero or sign extended
    
    This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
    constant element number to be zero extended.  It also allows vec_extract of V4SI
    and V8HI vector types with constant element number to be sign extended.
    
    2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
            (vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
            (vsx_extract_v8hi_load_to_s<mode>): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
            * gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
            * gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
            * gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
            * gcc.target/powerpc/vec-extract-mem-short-2.c: New file.

Diff:
---
 .../gcc.target/powerpc/vec-extract-mem-char-1.c    | 35 +++++++++++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-int-1.c     | 35 +++++++++++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-int-2.c     | 36 ++++++++++++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-short-1.c   | 35 +++++++++++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-short-2.c   | 36 ++++++++++++++++++++++
 5 files changed, 177 insertions(+)

diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..61f021ee99f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   QImode and fold zero extension into the load.  */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+  return vec_extract (*p, 0);		/* lbz, no rlwinm.  */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+  return vec_extract (*p, 1);          /* lbz, no rlwinm.  */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+  return vec_extract (p[4], 0);		/* lbz, no rlwinm.  */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+  return vec_extract (p[4], 3);		/* lbz, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlbzx?\M}  4 } } */
+/* { dg-final { scan-assembler-not   {\mrlwinm\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e59ceae6866
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   SImode and fold zero extension into the load.  */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+  return vec_extract (*p, 0);          /* lwz, no rldicl.  */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+  return vec_extract (*p, 1);          /* lwz, no rldicl.  */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+  return vec_extract (p[4], 0);		/* lwz, no rldicl.  */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+  return vec_extract (p[4], 3);		/* lwz, no rldicl.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlwzx?\M}  4 } } */
+/* { dg-final { scan-assembler-not   {\mrldicl\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..052371e72ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   SImode and fold sign extension into the load.  */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+  return vec_extract (*p, 0);          /* lwa, no extsw.  */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+  return vec_extract (*p, 1);          /* lwa, no extsw.  */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+  return vec_extract (p[4], 0);		/* lwa, no extsw.  */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+  return vec_extract (p[4], 3);		/* lwa, no extsw.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
+/* { dg-final { scan-assembler-not   {\mlwzx?\M}   } } */
+/* { dg-final { scan-assembler-not   {\mextsw\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..65ae21b1a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   SImode and fold zero extension into the load.  */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+  return vec_extract (*p, 0);          /* lwz, no rlwinm.  */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+  return vec_extract (*p, 1);          /* lwz, no rlwinm.  */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+  return vec_extract (p[4], 0);		/* lbz, no rlwinm.  */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+  return vec_extract (p[4], 3);		/* lbz, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlhzx?\M}  4 } } */
+/* { dg-final { scan-assembler-not   {\mrlwinm\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..6a2f23cfc57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   HImode and fold sign extension into the load.  */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+  return vec_extract (*p, 0);          /* lwa, no extsw.  */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+  return vec_extract (*p, 1);          /* lwa, no extsw.  */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+  return vec_extract (p[4], 0);		/* lwa, no extsw.  */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+  return vec_extract (p[4], 3);		/* lwa, no extsw.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
+/* { dg-final { scan-assembler-not   {\mlhzx?\M}   } } */
+/* { dg-final { scan-assembler-not   {\mextsh\M}   } } */