[gcc(refs/users/meissner/heads/work120)] Allow consant element vec_extract to be loaded into vector registers.

[gcc(refs/users/meissner/heads/work120)] Allow consant element vec_extract to be loaded into vector registers.

[Michael Meissner]

https://gcc.gnu.org/g:ec1eabe58a6069d54b3396a5c771f84ba135b06e

commit ec1eabe58a6069d54b3396a5c771f84ba135b06e
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon May 1 17:14:53 2023 -0400

    Allow consant element vec_extract to be loaded into vector registers.
    
    This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
    constant element number to be loaded into vector registers directly.
    
    This patch also adds support for optimzing 0 element number to not need a base
    register tempoary.  Likewise, if we have an offsettable address, we don't need
    to allocate a scratch register.
    
    2023-05-01   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute.
            (vsx_extract_<mode>_load): Allow vector registers to be loaded.  Add
            optimizations for loading up element 0 and/or with an offsettable
            address.

Diff:
---
 gcc/config/rs6000/vsx.md | 38 +++++++++++++++++++++++++++++---------
 1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f42793fe012..bac7833d7de 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,6 +223,12 @@
 			  (V8HI  "v")
 			  (V4SI  "wa")])
 
+;; Mode attribute to give the isa constraint for accessing Altivec registers
+;; with vector extract and insert operations.
+(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
+			      (V8HI  "p9v")
+			      (V4SI  "p8v")])
+
 ;; Mode iterator for binary floating types other than double to
 ;; optimize convert to that floating point type from an extract
 ;; of an integer type
@@ -4008,23 +4014,37 @@
 }
   [(set_attr "type" "mfvsr")])
 
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
+;; number.  For vector registers, we require X-form addressing.
+;; Alternatives:
+;;       Reg:  Ele:  Cpu:   Addr:                 need scratch
+;;    1: GPR   0     any    normal address        no
+;;    2: GPR   1-3   any    offsettable address   no
+;;    3: GPR   1-3   any    single register       yes
+;;    4: wa/v  0     p8/p9  reg+reg or reg        no
+;;    5: wa/v  1-3   p8/p9  single register       yes
 (define_insn_and_split "*vsx_extract_<mode>_load"
-  [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "register_operand"
+			"=r,     r,     r,      wa,           wa")
 	(vec_select:<VEC_base>
-	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
-   (clobber (match_scratch:DI 3 "=&b"))]
+	 (match_operand:VSX_EXTRACT_I 1 "memory_operand"
+			"m,      o,     m,      Z,            Q")
+	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>"
+			"O,      n,     n,      O,            n")])))
+   (clobber (match_scratch:DI 3
+			"=X,     X,     &b,     X,            &b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
   [(set (match_dup 0) (match_dup 4))]
 {
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
-					   operands[3], <VEC_base>mode);
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+					   operands[2], operands[3],
+					   <VEC_base>mode);
 }
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
+  [(set_attr "type"	"load,   load,  load,   fpload,       fpload")
+   (set_attr "length"	"*,      *,     8,      *,            8")
+   (set_attr "isa"	"*,      *,     *,      <VSX_EX_ISA>, <VSX_EX_ISA>")])
 
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"