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* [gcc(refs/users/meissner/heads/work120)] Optimize sign and zero extension of vec_extract from memory with constant element
@ 2023-05-01 21:42 Michael Meissner
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From: Michael Meissner @ 2023-05-01 21:42 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3ab75878e878eac0765d31149682221345b9817e
commit 3ab75878e878eac0765d31149682221345b9817e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 1 17:42:22 2023 -0400
Optimize sign and zero extension of vec_extract from memory with constant element
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be zero extended. It also allows vec_extract of V4SI
and V8HI vector types with constant element number to be sign extended.
2023-05-01 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 93 ++++++++++++++++++++++
| 35 ++++++++
| 35 ++++++++
| 36 +++++++++
| 35 ++++++++
| 36 +++++++++
6 files changed, 270 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index bac7833d7de..9c3e07fbfce 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4046,6 +4046,99 @@
(set_attr "length" "*, *, 8, *, 8")
(set_attr "isa" "*, *, *, <VSX_EX_ISA>, <VSX_EX_ISA>")])
+;; Fold extracting a V4SI element with a constant element with either sign or
+;; zero extension to DImode.
+;; Alternatives:
+;; Reg: Ele: Addr: need scratch
+;; 1: GPR 0 normal address no
+;; 2: GPR 1-3 offsettable address no
+;; 3: GPR 1-3 single register yes
+;; 4: VSX 0 reg+reg or reg no
+;; 5: VSX 1-3 single register yes
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand"
+ "=r, r, r, wa, wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand"
+ "m, o, m, Z, Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand"
+ "O, n, n, O, n")]))))
+ (clobber (match_scratch:DI 3
+ "=X, X, &b, X, &b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load, load, load, fpload, fpload")
+ (set_attr "length" "*, *, 8, *, 8")])
+
+;; Fold extracting a V8HI/V4SI element with a constant element with zero
+;; extension to either DImode or SImode.
+;; Alternatives:
+;; Reg: Ele: Cpu: Addr: need scratch
+;; 1: GPR 0 any normal address no
+;; 2: GPR 1-3 any offsettable address no
+;; 3: GPR 1-3 any single register yes
+;; 4: VMX 0 p9 reg+reg or reg no
+;; 5: VMX 1-3 p9 single register yes
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand"
+ "=r, r, r, v, v")
+ (zero_extend:GPR
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand"
+ "m, o, m, Z, Q")
+ (parallel [(match_operand:QI 2 "const_int_operand"
+ "O, n, n, O, n")]))))
+ (clobber (match_scratch:DI 3
+ "=X, X, &b, X, &b"))]
+ "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:VEC_base>mode);
+}
+ [(set_attr "type" "load, load, load, fpload, fpload")
+ (set_attr "length" "*, *, 8, *, 8")
+ (set_attr "isa" "*, *, *, p9v, p9v")])
+
+;; Fold extracting a V8HI element with a constant element with sign extension
+;; to either DImode or SImode.
+;; Reg: Ele: Addr: need scratch
+;; 1: GPR 0 normal address no
+;; 2: GPR 1-3 offsettable address no
+;; 3: GPR 1-3 single register yes
+(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
+ (sign_extend:GPR
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,m")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "*,*,8")])
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..61f021ee99f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e59ceae6866
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..052371e72ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..65ae21b1a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..6a2f23cfc57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
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