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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work120)] Revert patches Date: Mon, 1 May 2023 23:01:14 +0000 (GMT) [thread overview] Message-ID: <20230501230114.2B9D83858D1E@sourceware.org> (raw) https://gcc.gnu.org/g:a77ad87e980b128cca1595578730f89cc8c8ebb1 commit a77ad87e980b128cca1595578730f89cc8c8ebb1 Author: Michael Meissner <meissner@linux.ibm.com> Date: Mon May 1 19:01:10 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/predicates.md | 13 ---------- gcc/config/rs6000/rs6000.cc | 57 ++++++++++++++--------------------------- gcc/config/rs6000/vsx.md | 24 ++++++++--------- 3 files changed, 31 insertions(+), 63 deletions(-) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 571386e7c21..a16ee30f0c0 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -994,19 +994,6 @@ return memory_operand (op, mode); }) -;; Return true if the address can be used in optimizing vec_extract from memory -;; operations. We don't allow update memory addresses or Altivec style vector -;; addresses. -(define_predicate "vec_extract_memory_operand" - (match_code "mem") -{ - if (update_address_mem (op, mode)) - return 0; - if (altivec_indexed_or_indirect_operand (op, mode)) - return 0; - return memory_operand (op, mode); -}) - ;; Return 1 if the operand is a MEM with an indexed-form address. (define_special_predicate "indexed_address_mem" (match_test "(MEM_P (op) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 0d1f4e7dfe3..6debf0f63ff 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size) if (CONST_INT_P (element)) return GEN_INT (INTVAL (element) * scalar_size); - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - - /* After register allocation, all insns should use the 'Q' constraint - (address is a single register) if the element number is not a - constant. */ - gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem)); + /* All insns should use the 'Q' constraint (address is a single register) if + the element number is not a constant. */ + gcc_assert (satisfies_constraint_Q (mem)); /* Mask the element to make sure the element number is between 0 and the maximum number of elements - 1 so that we don't generate an address @@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size) if (shift > 0) { rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift)); - if (can_create_pseudo_p ()) - base_tmp = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (base_tmp, shift_op)); } @@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp) else { - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - emit_move_insn (base_tmp, addr); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } @@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp) temporary (BASE_TMP) to fixup the address. Return the new memory address that is valid for reads or writes to a given register (SCALAR_REG). - The temporary BASE_TMP might be set multiple times with this code if this is - called after register allocation. */ + This function is expected to be called after reload is completed when we are + splitting insns. The temporary BASE_TMP might be set multiple times with + this code. */ rtx rs6000_adjust_vec_address (rtx scalar_reg, @@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg, rtx addr = XEXP (mem, 0); rtx new_addr; - if (GET_CODE (base_tmp) != SCRATCH) - { - gcc_assert (!reg_mentioned_p (base_tmp, addr)); - gcc_assert (!reg_mentioned_p (base_tmp, element)); - } + gcc_assert (!reg_mentioned_p (base_tmp, addr)); + gcc_assert (!reg_mentioned_p (base_tmp, element)); /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */ gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC); @@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg, offset, it has the benefit that if D-FORM instructions are allowed, the offset is part of the memory access to the vector element. */ - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1))); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } @@ -7863,30 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg, else { - rtx addr_reg = force_reg (Pmode, addr); - new_addr = gen_rtx_PLUS (Pmode, addr_reg, element_offset); + emit_move_insn (base_tmp, addr); + new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } - /* If register allocation has been done and the address isn't valid, move - the address into the temporary base register. Some reasons it could not - be valid include: + /* If the address isn't valid, move the address into the temporary base + register. Some reasons it could not be valid include: The address offset overflowed the 16 or 34 bit offset size; We need to use a DS-FORM load, and the bottom 2 bits are non-zero; We need to use a DQ-FORM load, and the bottom 4 bits are non-zero; Only X_FORM loads can be done, and the address is D_FORM. */ - if (!can_create_pseudo_p ()) - { - enum insn_form iform - = address_to_insn_form (new_addr, scalar_mode, - reg_to_non_prefixed (scalar_reg, scalar_mode)); + enum insn_form iform + = address_to_insn_form (new_addr, scalar_mode, + reg_to_non_prefixed (scalar_reg, scalar_mode)); - if (iform == INSN_FORM_BAD) - { - emit_move_insn (base_tmp, new_addr); - new_addr = base_tmp; - } + if (iform == INSN_FORM_BAD) + { + emit_move_insn (base_tmp, new_addr); + new_addr = base_tmp; } return change_address (mem, scalar_mode, new_addr); diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 73f872d9487..410183dde93 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4027,7 +4027,7 @@ [(set (match_operand:<VEC_base> 0 "register_operand" "=r, r, r, wa, wa") (vec_select:<VEC_base> - (match_operand:VSX_EXTRACT_I 1 "vec_extract_memory_operand" + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m, o, m, Z, Q") (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "O, n, n, O, n")]))) @@ -4035,7 +4035,7 @@ "=X, X, &b, X, &b"))] "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], @@ -4060,7 +4060,7 @@ "=r, r, r, wa, wa") (any_extend:DI (vec_select:SI - (match_operand:V4SI 1 "vec_extract_memory_operand" + (match_operand:V4SI 1 "memory_operand" "m, o, m, Z, Q") (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O, n, n, O, n")])))) @@ -4068,7 +4068,7 @@ "=X, X, &b, X, &b"))] "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (any_extend:DI (match_dup 4)))] { @@ -4093,7 +4093,7 @@ "=r, r, r, v, v") (zero_extend:GPR (vec_select:<VEC_base> - (match_operand:VSX_EXTRACT_I2 1 "vec_extract_memory_operand" + (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m, o, m, Z, Q") (parallel [(match_operand:QI 2 "const_int_operand" "O, n, n, O, n")])))) @@ -4101,7 +4101,7 @@ "=X, X, &b, X, &b"))] "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (zero_extend:GPR (match_dup 4)))] { @@ -4173,12 +4173,12 @@ [(set (match_operand:GPR 0 "register_operand" "=r,r,r") (sign_extend:GPR (vec_select:HI - (match_operand:V8HI 1 "vec_extract_memory_operand" "m,o,m") + (match_operand:V8HI 1 "memory_operand" "m,o,m") (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")])))) (clobber (match_scratch:DI 3 "=X,X,&b"))] "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (sign_extend:GPR (match_dup 4)))] { @@ -4219,7 +4219,7 @@ (clobber (match_scratch:DI 3 "=&b,&b"))] "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], @@ -4240,7 +4240,7 @@ (clobber (match_scratch:DI 3 "=&b,&b"))] "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (any_extend:DI (match_dup 4)))] { @@ -4262,7 +4262,7 @@ (clobber (match_scratch:DI 3 "=&b,&b"))] "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (zero_extend:GPR (match_dup 4)))] { @@ -4285,7 +4285,7 @@ (clobber (match_scratch:DI 3 "=&b"))] "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (sign_extend:GPR (match_dup 4)))] {
next reply other threads:[~2023-05-01 23:01 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-01 23:01 Michael Meissner [this message] -- strict thread matches above, loose matches on Subject: below -- 2023-05-02 1:38 Michael Meissner 2023-05-01 23:08 Michael Meissner 2023-05-01 20:23 Michael Meissner 2023-05-01 20:20 Michael Meissner
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