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* [gcc(refs/users/meissner/heads/work120)] Revert patches
@ 2023-05-01 23:01 Michael Meissner
0 siblings, 0 replies; 5+ messages in thread
From: Michael Meissner @ 2023-05-01 23:01 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a77ad87e980b128cca1595578730f89cc8c8ebb1
commit a77ad87e980b128cca1595578730f89cc8c8ebb1
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 1 19:01:10 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/predicates.md | 13 ----------
gcc/config/rs6000/rs6000.cc | 57 ++++++++++++++---------------------------
gcc/config/rs6000/vsx.md | 24 ++++++++---------
3 files changed, 31 insertions(+), 63 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 571386e7c21..a16ee30f0c0 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -994,19 +994,6 @@
return memory_operand (op, mode);
})
-;; Return true if the address can be used in optimizing vec_extract from memory
-;; operations. We don't allow update memory addresses or Altivec style vector
-;; addresses.
-(define_predicate "vec_extract_memory_operand"
- (match_code "mem")
-{
- if (update_address_mem (op, mode))
- return 0;
- if (altivec_indexed_or_indirect_operand (op, mode))
- return 0;
- return memory_operand (op, mode);
-})
-
;; Return 1 if the operand is a MEM with an indexed-form address.
(define_special_predicate "indexed_address_mem"
(match_test "(MEM_P (op)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0d1f4e7dfe3..6debf0f63ff 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,30 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- rtx addr_reg = force_reg (Pmode, addr);
- new_addr = gen_rtx_PLUS (Pmode, addr_reg, element_offset);
+ emit_move_insn (base_tmp, addr);
+ new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 73f872d9487..410183dde93 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4027,7 +4027,7 @@
[(set (match_operand:<VEC_base> 0 "register_operand"
"=r, r, r, wa, wa")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "vec_extract_memory_operand"
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand"
"m, o, m, Z, Q")
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>"
"O, n, n, O, n")])))
@@ -4035,7 +4035,7 @@
"=X, X, &b, X, &b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
@@ -4060,7 +4060,7 @@
"=r, r, r, wa, wa")
(any_extend:DI
(vec_select:SI
- (match_operand:V4SI 1 "vec_extract_memory_operand"
+ (match_operand:V4SI 1 "memory_operand"
"m, o, m, Z, Q")
(parallel [(match_operand:QI 2 "const_0_to_3_operand"
"O, n, n, O, n")]))))
@@ -4068,7 +4068,7 @@
"=X, X, &b, X, &b"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(any_extend:DI (match_dup 4)))]
{
@@ -4093,7 +4093,7 @@
"=r, r, r, v, v")
(zero_extend:GPR
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "vec_extract_memory_operand"
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand"
"m, o, m, Z, Q")
(parallel [(match_operand:QI 2 "const_int_operand"
"O, n, n, O, n")]))))
@@ -4101,7 +4101,7 @@
"=X, X, &b, X, &b"))]
"VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(zero_extend:GPR (match_dup 4)))]
{
@@ -4173,12 +4173,12 @@
[(set (match_operand:GPR 0 "register_operand" "=r,r,r")
(sign_extend:GPR
(vec_select:HI
- (match_operand:V8HI 1 "vec_extract_memory_operand" "m,o,m")
+ (match_operand:V8HI 1 "memory_operand" "m,o,m")
(parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
(clobber (match_scratch:DI 3 "=X,X,&b"))]
"VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(sign_extend:GPR (match_dup 4)))]
{
@@ -4219,7 +4219,7 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
@@ -4240,7 +4240,7 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(any_extend:DI (match_dup 4)))]
{
@@ -4262,7 +4262,7 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(zero_extend:GPR (match_dup 4)))]
{
@@ -4285,7 +4285,7 @@
(clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(sign_extend:GPR (match_dup 4)))]
{
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/meissner/heads/work120)] Revert patches
@ 2023-05-02 1:38 Michael Meissner
0 siblings, 0 replies; 5+ messages in thread
From: Michael Meissner @ 2023-05-02 1:38 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:855f36f324a85cc11435901e4369e37917f2cdad
commit 855f36f324a85cc11435901e4369e37917f2cdad
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 1 21:38:41 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 52 ------------------------------------------------
1 file changed, 52 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 410183dde93..47e5a9c4709 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4295,58 +4295,6 @@
}
[(set_attr "type" "load")])
-;; Fold extracting a V4SI element with a variable element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (any_float:SFDF
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q")
- (match_operand:DI 2 "register_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
-;; Fold extracting a V8HI/V16QI element with a variable element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unsigned_float:SFDF
- (unspec:<VSX_EXTRACT_I2:VEC_base>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q")
- (match_operand:DI 2 "register_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/meissner/heads/work120)] Revert patches
@ 2023-05-01 23:08 Michael Meissner
0 siblings, 0 replies; 5+ messages in thread
From: Michael Meissner @ 2023-05-01 23:08 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:956989a0739cb47c07498de4348673980ae3ee46
commit 956989a0739cb47c07498de4348673980ae3ee46
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 1 19:08:45 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/predicates.md | 13 ----------
gcc/config/rs6000/rs6000.cc | 57 ++++++++++++++---------------------------
gcc/config/rs6000/vsx.md | 32 +++++++++++------------
3 files changed, 35 insertions(+), 67 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 571386e7c21..a16ee30f0c0 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -994,19 +994,6 @@
return memory_operand (op, mode);
})
-;; Return true if the address can be used in optimizing vec_extract from memory
-;; operations. We don't allow update memory addresses or Altivec style vector
-;; addresses.
-(define_predicate "vec_extract_memory_operand"
- (match_code "mem")
-{
- if (update_address_mem (op, mode))
- return 0;
- if (altivec_indexed_or_indirect_operand (op, mode))
- return 0;
- return memory_operand (op, mode);
-})
-
;; Return 1 if the operand is a MEM with an indexed-form address.
(define_special_predicate "indexed_address_mem"
(match_test "(MEM_P (op)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0d1f4e7dfe3..6debf0f63ff 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,30 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- rtx addr_reg = force_reg (Pmode, addr);
- new_addr = gen_rtx_PLUS (Pmode, addr_reg, element_offset);
+ emit_move_insn (base_tmp, addr);
+ new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e227d875dfb..410183dde93 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4027,7 +4027,7 @@
[(set (match_operand:<VEC_base> 0 "register_operand"
"=r, r, r, wa, wa")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "vec_extract_memory_operand"
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand"
"m, o, m, Z, Q")
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>"
"O, n, n, O, n")])))
@@ -4035,7 +4035,7 @@
"=X, X, &b, X, &b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
@@ -4060,7 +4060,7 @@
"=r, r, r, wa, wa")
(any_extend:DI
(vec_select:SI
- (match_operand:V4SI 1 "vec_extract_memory_operand"
+ (match_operand:V4SI 1 "memory_operand"
"m, o, m, Z, Q")
(parallel [(match_operand:QI 2 "const_0_to_3_operand"
"O, n, n, O, n")]))))
@@ -4068,7 +4068,7 @@
"=X, X, &b, X, &b"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(any_extend:DI (match_dup 4)))]
{
@@ -4093,7 +4093,7 @@
"=r, r, r, v, v")
(zero_extend:GPR
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "vec_extract_memory_operand"
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand"
"m, o, m, Z, Q")
(parallel [(match_operand:QI 2 "const_int_operand"
"O, n, n, O, n")]))))
@@ -4101,7 +4101,7 @@
"=X, X, &b, X, &b"))]
"VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(zero_extend:GPR (match_dup 4)))]
{
@@ -4173,12 +4173,12 @@
[(set (match_operand:GPR 0 "register_operand" "=r,r,r")
(sign_extend:GPR
(vec_select:HI
- (match_operand:V8HI 1 "vec_extract_memory_operand" "m,o,m")
+ (match_operand:V8HI 1 "memory_operand" "m,o,m")
(parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
(clobber (match_scratch:DI 3 "=X,X,&b"))]
"VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(sign_extend:GPR (match_dup 4)))]
{
@@ -4213,13 +4213,13 @@
(define_insn_and_split "*vsx_extract_<mode>_var_load"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,wa")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "vec_extract_memory_operand" "Q,Q")
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
@@ -4234,13 +4234,13 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
(any_extend:DI
(unspec:SI
- [(match_operand:V4SI 1 "vec_extract_memory_operand" "Q,Q")
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT)))
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(any_extend:DI (match_dup 4)))]
{
@@ -4256,13 +4256,13 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,wa")
(zero_extend:GPR
(unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "vec_extract_memory_operand" "Q,Q")
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT)))
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(zero_extend:GPR (match_dup 4)))]
{
@@ -4279,13 +4279,13 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(sign_extend:GPR
(unspec:HI
- [(match_operand:V8HI 1 "vec_extract_memory_operand" "Q")
+ [(match_operand:V8HI 1 "memory_operand" "Q")
(match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT)))
(clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(sign_extend:GPR (match_dup 4)))]
{
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/meissner/heads/work120)] Revert patches
@ 2023-05-01 20:23 Michael Meissner
0 siblings, 0 replies; 5+ messages in thread
From: Michael Meissner @ 2023-05-01 20:23 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1390e2d93a8cb81edd143dc50e218c900fb3834d
commit 1390e2d93a8cb81edd143dc50e218c900fb3834d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 1 16:23:31 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..d615474df01 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,7 +3549,7 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-(define_insn_and_split "*vsx_extract_v4sf_load"
+(define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
(match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/meissner/heads/work120)] Revert patches
@ 2023-05-01 20:20 Michael Meissner
0 siblings, 0 replies; 5+ messages in thread
From: Michael Meissner @ 2023-05-01 20:20 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:08186cfb5f1671eba5cf909e72946171825ec759
commit 08186cfb5f1671eba5cf909e72946171825ec759
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 1 16:20:03 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 52 ---------------------------------------------
1 file changed, 52 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7d6c94aee5b..0e1f4cb3868 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -986,58 +986,6 @@
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_insn_and_split "zero_extendditi2"
- [(set (match_operand:TI 0 "gpc_reg_operand" "=r,r,wa,wa,wa")
- (zero_extend:TI
- (match_operand:DI 1 "reg_or_mem_operand" "r,m,b,Z,wa")))
- (clobber (match_scratch:DI 2 "=&X,X,X,X,wa"))]
- "TARGET_POWERPC64 && TARGET_P9_VECTOR"
- "@
- #
- #
- mtvsrdd %x0,0,%1
- lxvrdx %x0,%y1
- #"
- "&& reload_completed
- && (int_reg_operand (operands[0], TImode)
- || (vsx_register_operand (operands[0], TImode)
- && vsx_register_operand (operands[1], DImode)))"
- [(set (match_dup 2) (match_dup 1))
- (set (match_dup 3) (const_int 0))]
-{
- rtx dest = operands[0];
- rtx src = operands[1];
-
- /* If we are converting a VSX DImode to VSX TImode, we need to move the upper
- 64-bits (DImode) to the lower 64-bits. We can't just do a xxpermdi
- instruction to swap the two 64-bit words, because can't rely on the bottom
- 64-bits of the VSX register being 0. Instead we create a 0 and do the
- xxpermdi operation to combine the two registers. */
- if (vsx_register_operand (dest, TImode)
- && vsx_register_operand (src, DImode))
- {
- rtx tmp = operands[2];
- emit_move_insn (tmp, const0_rtx);
-
- rtx hi = tmp;
- rtx lo = src;
- if (!BYTES_BIG_ENDIAN)
- std::swap (hi, lo);
-
- rtx dest_v2di = gen_rtx_REG (V2DImode, reg_or_subregno (dest));
- emit_insn (gen_vsx_concat_v2di (dest_v2di, hi, lo));
- DONE;
- }
-
- /* If we are zero extending to a GPR register either from a GPR register,
- a VSX register or from memory, do the zero extend operation to the
- lower DI register, and set the upper DI register to 0. */
- operands[2] = gen_lowpart (DImode, dest);
- operands[3] = gen_highpart (DImode, dest);
-}
- [(set_attr "type" "*,load,vecexts,vecload,vecperm")
- (set_attr "isa" "*,*,p9v,p10,*")
- (set_attr "length" "8,8,*,*,8")])
(define_insn "extendqi<mode>2"
[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v")
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-05-02 1:38 UTC | newest]
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