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* [gcc r14-402] RISC-V: Add AMO release bits
@ 2023-05-02 20:10 Patrick O'Neill
0 siblings, 0 replies; only message in thread
From: Patrick O'Neill @ 2023-05-02 20:10 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a61a067b15221de981afd4df8433e96a8cf32341
commit r14-402-ga61a067b15221de981afd4df8433e96a8cf32341
Author: Patrick O'Neill <patrick@rivosinc.com>
Date: Wed Apr 5 09:47:05 2023 -0700
RISC-V: Add AMO release bits
This patch sets the relevant .rl bits on amo operations.
2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Change behavior
of %A to include release bits.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Diff:
---
gcc/config/riscv/riscv.cc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 11af780fc3e..f8bc402e35a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4508,8 +4508,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
break;
case 'A':
- if (riscv_memmodel_needs_amo_acquire (model))
+ if (riscv_memmodel_needs_amo_acquire (model)
+ && riscv_memmodel_needs_release_fence (model))
+ fputs (".aqrl", file);
+ else if (riscv_memmodel_needs_amo_acquire (model))
fputs (".aq", file);
+ else if (riscv_memmodel_needs_release_fence (model))
+ fputs (".rl", file);
break;
case 'F':
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