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* [gcc r14-1440] RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)
@ 2023-05-31 13:54 Pan Li
0 siblings, 0 replies; only message in thread
From: Pan Li @ 2023-05-31 13:54 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:57920ae9653e8ef2b3f5f68c22894f5e65a3673d
commit r14-1440-g57920ae9653e8ef2b3f5f68c22894f5e65a3673d
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Wed May 31 18:35:10 2023 +0800
RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)
Base on the discussion here:
https://github.com/riscv/riscv-v-spec/issues/884
vfwcvt doesn't depend on FRM. So remove FRM preparing for mode switching support.
gcc/ChangeLog:
* config/riscv/vector.md: Remove FRM.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diff:
---
gcc/config/riscv/vector.md | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cb4e77e7854..cd41ebbb24f 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7178,10 +7178,8 @@
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)
- (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
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