[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)

[Jeff Law]

https://gcc.gnu.org/g:94d27ee54f4d6a48f3c28b2183f8fa1992b3a239

commit 94d27ee54f4d6a48f3c28b2183f8fa1992b3a239
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Wed May 31 18:35:10 2023 +0800

    RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)
    
    Base on the discussion here:
    https://github.com/riscv/riscv-v-spec/issues/884
    
    vfwcvt doesn't depend on FRM. So remove FRM preparing for mode switching support.
    
    gcc/ChangeLog:
    
            * config/riscv/vector.md: Remove FRM.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>

Diff:
---
 gcc/config/riscv/vector.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cb4e77e7854..cd41ebbb24f 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7178,10 +7178,8 @@
 	     (match_operand 5 "const_int_operand"                 "    i,    i")
 	     (match_operand 6 "const_int_operand"                 "    i,    i")
 	     (match_operand 7 "const_int_operand"                 "    i,    i")
-	     (match_operand 8 "const_int_operand"                 "    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)
-	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (float_extend:VWEXTF
 	     (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
 	  (match_operand:VWEXTF 2 "vector_merge_operand"          "   vu,    0")))]

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)

[Jeff Law]

https://gcc.gnu.org/g:5d2c19e24e40f8a1137d0e0346b221da775580a7

commit 5d2c19e24e40f8a1137d0e0346b221da775580a7
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Wed May 31 18:35:10 2023 +0800

    RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)
    
    Base on the discussion here:
    https://github.com/riscv/riscv-v-spec/issues/884
    
    vfwcvt doesn't depend on FRM. So remove FRM preparing for mode switching support.
    
    gcc/ChangeLog:
    
            * config/riscv/vector.md: Remove FRM.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>

Diff:
---
 gcc/config/riscv/vector.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cb4e77e7854..cd41ebbb24f 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7178,10 +7178,8 @@
 	     (match_operand 5 "const_int_operand"                 "    i,    i")
 	     (match_operand 6 "const_int_operand"                 "    i,    i")
 	     (match_operand 7 "const_int_operand"                 "    i,    i")
-	     (match_operand 8 "const_int_operand"                 "    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)
-	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (float_extend:VWEXTF
 	     (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
 	  (match_operand:VWEXTF 2 "vector_merge_operand"          "   vu,    0")))]