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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add test for vfloat16*_t (non tuple) types
@ 2023-06-05 16:17 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-06-05 16:17 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:22ddc614b3cd6eebe7121eb646f96b0345dd0f7e
commit 22ddc614b3cd6eebe7121eb646f96b0345dd0f7e
Author: Pan Li <pan2.li@intel.com>
Date: Thu Jun 1 19:10:04 2023 +0800
RISC-V: Add test for vfloat16*_t (non tuple) types
This patch would like to add some test cases of vfloat16*_t (non tuple),
no 'zvfh' or 'zvfhmin' will meet unknown type.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-16.c: Add test cases.
* gcc.target/riscv/rvv/base/user-7.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c | 6 ++++++
gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
index be2cbb5efd7..9e962a70acf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
@@ -173,6 +173,12 @@ void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { dg-error {unknown type n
void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */
void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name '__rvv_int64m4x2_t'} } */
void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */
+void f___rvv_float16mf4_t () {__rvv_float16mf4_t t;} /* { dg-error {unknown type name '__rvv_float16mf4_t'} } */
+void f___rvv_float16mf2_t () {__rvv_float16mf2_t t;} /* { dg-error {unknown type name '__rvv_float16mf2_t'} } */
+void f___rvv_float16m1_t () {__rvv_float16m1_t t;} /* { dg-error {unknown type name '__rvv_float16m1_t'} } */
+void f___rvv_float16m2_t () {__rvv_float16m2_t t;} /* { dg-error {unknown type name '__rvv_float16m2_t'} } */
+void f___rvv_float16m4_t () {__rvv_float16m4_t t;} /* { dg-error {unknown type name '__rvv_float16m4_t'} } */
+void f___rvv_float16m8_t () {__rvv_float16m8_t t;} /* { dg-error {unknown type name '__rvv_float16m8_t'} } */
void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;}
void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;}
void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
index 2172a5c7c79..0620a728208 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
@@ -173,6 +173,12 @@ void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint6
void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */
void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */
void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */
+void f_vfloat16mf4_t () {vfloat16mf4_t t;} /* { dg-error {unknown type name 'vfloat16mf4_t'} } */
+void f_vfloat16mf2_t () {vfloat16mf2_t t;} /* { dg-error {unknown type name 'vfloat16mf2_t'} } */
+void f_vfloat16m1_t () {vfloat16m1_t t;} /* { dg-error {unknown type name 'vfloat16m1_t'} } */
+void f_vfloat16m2_t () {vfloat16m2_t t;} /* { dg-error {unknown type name 'vfloat16m2_t'} } */
+void f_vfloat16m4_t () {vfloat16m4_t t;} /* { dg-error {unknown type name 'vfloat16m4_t'} } */
+void f_vfloat16m8_t () {vfloat16m8_t t;} /* { dg-error {unknown type name 'vfloat16m8_t'} } */
void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */
void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */
void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add test for vfloat16*_t (non tuple) types
@ 2023-07-14 2:42 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-07-14 2:42 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:987d08b99db4c4d72fc2e7e3351a65e8ba9a4080
commit 987d08b99db4c4d72fc2e7e3351a65e8ba9a4080
Author: Pan Li <pan2.li@intel.com>
Date: Thu Jun 1 19:10:04 2023 +0800
RISC-V: Add test for vfloat16*_t (non tuple) types
This patch would like to add some test cases of vfloat16*_t (non tuple),
no 'zvfh' or 'zvfhmin' will meet unknown type.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-16.c: Add test cases.
* gcc.target/riscv/rvv/base/user-7.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c | 6 ++++++
gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
index be2cbb5efd7..9e962a70acf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
@@ -173,6 +173,12 @@ void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { dg-error {unknown type n
void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */
void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name '__rvv_int64m4x2_t'} } */
void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */
+void f___rvv_float16mf4_t () {__rvv_float16mf4_t t;} /* { dg-error {unknown type name '__rvv_float16mf4_t'} } */
+void f___rvv_float16mf2_t () {__rvv_float16mf2_t t;} /* { dg-error {unknown type name '__rvv_float16mf2_t'} } */
+void f___rvv_float16m1_t () {__rvv_float16m1_t t;} /* { dg-error {unknown type name '__rvv_float16m1_t'} } */
+void f___rvv_float16m2_t () {__rvv_float16m2_t t;} /* { dg-error {unknown type name '__rvv_float16m2_t'} } */
+void f___rvv_float16m4_t () {__rvv_float16m4_t t;} /* { dg-error {unknown type name '__rvv_float16m4_t'} } */
+void f___rvv_float16m8_t () {__rvv_float16m8_t t;} /* { dg-error {unknown type name '__rvv_float16m8_t'} } */
void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;}
void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;}
void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
index 2172a5c7c79..0620a728208 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
@@ -173,6 +173,12 @@ void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint6
void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */
void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */
void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */
+void f_vfloat16mf4_t () {vfloat16mf4_t t;} /* { dg-error {unknown type name 'vfloat16mf4_t'} } */
+void f_vfloat16mf2_t () {vfloat16mf2_t t;} /* { dg-error {unknown type name 'vfloat16mf2_t'} } */
+void f_vfloat16m1_t () {vfloat16m1_t t;} /* { dg-error {unknown type name 'vfloat16m1_t'} } */
+void f_vfloat16m2_t () {vfloat16m2_t t;} /* { dg-error {unknown type name 'vfloat16m2_t'} } */
+void f_vfloat16m4_t () {vfloat16m4_t t;} /* { dg-error {unknown type name 'vfloat16m4_t'} } */
+void f_vfloat16m8_t () {vfloat16m8_t t;} /* { dg-error {unknown type name 'vfloat16m8_t'} } */
void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */
void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */
void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-06-05 16:17 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add test for vfloat16*_t (non tuple) types Jeff Law
2023-07-14 2:42 Jeff Law
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