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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c
@ 2023-06-05 16:18 Jeff Law
0 siblings, 0 replies; 3+ messages in thread
From: Jeff Law @ 2023-06-05 16:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a3a7e8e1fd4171086f897e026a78d3baef9e8941
commit a3a7e8e1fd4171086f897e026a78d3baef9e8941
Author: Liao Shihua <shihua@iscas.ac.cn>
Date: Mon Jun 5 10:14:45 2023 -0600
Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c
I find fail of the xtheadcondmov-indirect-rv64.c test case and provide a way to solve it.
In this patch, I take Kito's advice that I modify the form of the function bodies.It likes
*[a-x0-9].
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadcondmov-indirect-rv32.c: Generalize to be
less sensitive to register allocation choices.
* gcc.target/riscv/xtheadcondmov-indirect-rv64.c: Similarly.
Diff:
---
.../gcc.target/riscv/xtheadcondmov-indirect-rv32.c | 50 +++++++++++-----------
.../gcc.target/riscv/xtheadcondmov-indirect-rv64.c | 50 +++++++++++-----------
2 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
index e2b135f3d00..d0df59c5e1c 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
@@ -5,9 +5,9 @@
/*
**ConEmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,10
-** th.mvnez a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_imm_reg(int x, int y){
@@ -17,9 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){
/*
**ConEmv_imm_reg_reg:
-** addi a5,a0,-1000
-** th.mveqz a2,a1,a5
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_reg_reg(int x, int y, int z){
@@ -29,9 +29,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z){
/*
**ConEmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mvnez a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_imm_reg(int x, int y, int z){
@@ -41,9 +41,9 @@ int ConEmv_reg_imm_reg(int x, int y, int z){
/*
**ConEmv_reg_reg_reg:
-** sub a1,a0,a1
-** th.mveqz a3,a2,a1
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_reg_reg(int x, int y, int z, int n){
@@ -53,10 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){
/*
**ConNmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,9998336
-** addi a0,a0,1664
-** th.mveqz a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,9998336+
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_imm_reg(int x, int y){
@@ -66,9 +66,9 @@ int ConNmv_imm_imm_reg(int x, int y){
/*
**ConNmv_imm_reg_reg:
-** addi a0,a0,-1000
-** th.mvnez a2,a1,a0
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_reg_reg(int x, int y, int z){
@@ -78,9 +78,9 @@ int ConNmv_imm_reg_reg(int x, int y, int z){
/*
**ConNmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mveqz a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_imm_reg(int x, int y, int z){
@@ -90,9 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){
/*
**ConNmv_reg_reg_reg:
-** sub a0,a0,a1
-** th.mvnez a3,a2,a0
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_reg_reg(int x, int y, int z, int n){
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
index 99956f8496c..cc971a75ace 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
@@ -5,9 +5,9 @@
/*
**ConEmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,10
-** th.mvnez a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_imm_reg(int x, int y){
@@ -17,9 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){
/*
**ConEmv_imm_reg_reg:
-** addi a0,a0,-1000
-** th.mveqz a2,a1,a5
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_reg_reg(int x, int y, int z){
@@ -29,9 +29,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z){
/*
**ConEmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mvnez a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_imm_reg(int x, int y, int z){
@@ -41,9 +41,9 @@ int ConEmv_reg_imm_reg(int x, int y, int z){
/*
**ConEmv_reg_reg_reg:
-** sub a1,a0,a1
-** th.mveqz a3,a2,a1
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_reg_reg(int x, int y, int z, int n){
@@ -53,10 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){
/*
**ConNmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,9998336
-** addi a0,a0,1664
-** th.mveqz a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,9998336+
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_imm_reg(int x, int y){
@@ -66,9 +66,9 @@ int ConNmv_imm_imm_reg(int x, int y){
/*
**ConNmv_imm_reg_reg:
-** addi a5,a0,-1000
-** th.mvnez a2,a1,a0
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_reg_reg(int x, int y, int z){
@@ -78,9 +78,9 @@ int ConNmv_imm_reg_reg(int x, int y, int z){
/*
**ConNmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mveqz a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_imm_reg(int x, int y, int z){
@@ -90,9 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){
/*
**ConNmv_reg_reg_reg:
-** sub a0,a0,a1
-** th.mvnez a3,a2,a0
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_reg_reg(int x, int y, int z, int n){
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c
@ 2023-07-14 2:43 Jeff Law
0 siblings, 0 replies; 3+ messages in thread
From: Jeff Law @ 2023-07-14 2:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:69a68db2ad7d9539a2a174209643b9d5f5a339e9
commit 69a68db2ad7d9539a2a174209643b9d5f5a339e9
Author: Liao Shihua <shihua@iscas.ac.cn>
Date: Mon Jun 5 10:14:45 2023 -0600
Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c
I find fail of the xtheadcondmov-indirect-rv64.c test case and provide a way to solve it.
In this patch, I take Kito's advice that I modify the form of the function bodies.It likes
*[a-x0-9].
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadcondmov-indirect-rv32.c: Generalize to be
less sensitive to register allocation choices.
* gcc.target/riscv/xtheadcondmov-indirect-rv64.c: Similarly.
Diff:
---
.../gcc.target/riscv/xtheadcondmov-indirect-rv32.c | 50 +++++++++++-----------
.../gcc.target/riscv/xtheadcondmov-indirect-rv64.c | 50 +++++++++++-----------
2 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
index e2b135f3d00..d0df59c5e1c 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
@@ -5,9 +5,9 @@
/*
**ConEmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,10
-** th.mvnez a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_imm_reg(int x, int y){
@@ -17,9 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){
/*
**ConEmv_imm_reg_reg:
-** addi a5,a0,-1000
-** th.mveqz a2,a1,a5
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_reg_reg(int x, int y, int z){
@@ -29,9 +29,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z){
/*
**ConEmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mvnez a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_imm_reg(int x, int y, int z){
@@ -41,9 +41,9 @@ int ConEmv_reg_imm_reg(int x, int y, int z){
/*
**ConEmv_reg_reg_reg:
-** sub a1,a0,a1
-** th.mveqz a3,a2,a1
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_reg_reg(int x, int y, int z, int n){
@@ -53,10 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){
/*
**ConNmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,9998336
-** addi a0,a0,1664
-** th.mveqz a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,9998336+
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_imm_reg(int x, int y){
@@ -66,9 +66,9 @@ int ConNmv_imm_imm_reg(int x, int y){
/*
**ConNmv_imm_reg_reg:
-** addi a0,a0,-1000
-** th.mvnez a2,a1,a0
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_reg_reg(int x, int y, int z){
@@ -78,9 +78,9 @@ int ConNmv_imm_reg_reg(int x, int y, int z){
/*
**ConNmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mveqz a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_imm_reg(int x, int y, int z){
@@ -90,9 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){
/*
**ConNmv_reg_reg_reg:
-** sub a0,a0,a1
-** th.mvnez a3,a2,a0
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_reg_reg(int x, int y, int z, int n){
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
index 99956f8496c..cc971a75ace 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
@@ -5,9 +5,9 @@
/*
**ConEmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,10
-** th.mvnez a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_imm_reg(int x, int y){
@@ -17,9 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){
/*
**ConEmv_imm_reg_reg:
-** addi a0,a0,-1000
-** th.mveqz a2,a1,a5
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_reg_reg(int x, int y, int z){
@@ -29,9 +29,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z){
/*
**ConEmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mvnez a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_imm_reg(int x, int y, int z){
@@ -41,9 +41,9 @@ int ConEmv_reg_imm_reg(int x, int y, int z){
/*
**ConEmv_reg_reg_reg:
-** sub a1,a0,a1
-** th.mveqz a3,a2,a1
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_reg_reg(int x, int y, int z, int n){
@@ -53,10 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){
/*
**ConNmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,9998336
-** addi a0,a0,1664
-** th.mveqz a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,9998336+
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_imm_reg(int x, int y){
@@ -66,9 +66,9 @@ int ConNmv_imm_imm_reg(int x, int y){
/*
**ConNmv_imm_reg_reg:
-** addi a5,a0,-1000
-** th.mvnez a2,a1,a0
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_reg_reg(int x, int y, int z){
@@ -78,9 +78,9 @@ int ConNmv_imm_reg_reg(int x, int y, int z){
/*
**ConNmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mveqz a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_imm_reg(int x, int y, int z){
@@ -90,9 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){
/*
**ConNmv_reg_reg_reg:
-** sub a0,a0,a1
-** th.mvnez a3,a2,a0
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_reg_reg(int x, int y, int z, int n){
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c
@ 2023-05-31 15:31 Jeff Law
0 siblings, 0 replies; 3+ messages in thread
From: Jeff Law @ 2023-05-31 15:31 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:254ca311953bf4bf6838b83c531921bd6720b106
commit 254ca311953bf4bf6838b83c531921bd6720b106
Author: Liao Shihua <shihua@iscas.ac.cn>
Date: Wed May 31 09:30:35 2023 -0600
Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c
I find fail of the xtheadcondmov-indirect-rv64.c test case and provide a way to solve it.
In this patch, I take Kito's advice that I modify the form of the function bodies.It likes
*[a-x0-9].
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadcondmov-indirect-rv32.c: Generalize to be
less sensitive to register allocation choices.
* gcc.target/riscv/xtheadcondmov-indirect-rv64.c: Similarly.
Diff:
---
gcc/testsuite/gcc.target/riscv/HEAD~175 | 39 +++++++++++
gcc/testsuite/gcc.target/riscv/shift-and-2.c | 19 +++++
gcc/testsuite/gcc.target/riscv/shift-shift-2.c | 5 +-
gcc/testsuite/gcc.target/riscv/sign-extend.c | 81 ++++++++++++++++++++++
.../gcc.target/riscv/xtheadcondmov-indirect-rv32.c | 50 ++++++-------
.../gcc.target/riscv/xtheadcondmov-indirect-rv64.c | 50 ++++++-------
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c | 3 +-
7 files changed, 194 insertions(+), 53 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/HEAD~175 b/gcc/testsuite/gcc.target/riscv/HEAD~175
new file mode 100644
index 00000000000..589f292ab50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/HEAD~175
@@ -0,0 +1,39 @@
+# This viminfo file was generated by Vim 9.0.
+# You may edit it if you're careful!
+
+# Viminfo version
+|1,4
+
+# Value of 'encoding' when this file was written
+*encoding=utf-8
+
+
+# hlsearch on (H) or off (h):
+~H
+# Command Line History (newest to oldest):
+:q
+|2,0,1685042995,,"q"
+
+# Search String History (newest to oldest):
+
+# Expression History (newest to oldest):
+
+# Input Line History (newest to oldest):
+
+# Debug Line History (newest to oldest):
+
+# Registers:
+
+# File marks:
+'0 1 0 ~/test/gcc/gcc/testsuite/gcc.target/riscv/rebase
+|4,48,1,0,1685042995,"~/test/gcc/gcc/testsuite/gcc.target/riscv/rebase"
+
+# Jumplist (newest first):
+-' 1 0 ~/test/gcc/gcc/testsuite/gcc.target/riscv/rebase
+|4,39,1,0,1685042995,"~/test/gcc/gcc/testsuite/gcc.target/riscv/rebase"
+
+# History of marks within files (newest to oldest):
+
+> ~/test/gcc/gcc/testsuite/gcc.target/riscv/rebase
+ * 1685042992 0
+ " 1 0
diff --git a/gcc/testsuite/gcc.target/riscv/shift-and-2.c b/gcc/testsuite/gcc.target/riscv/shift-and-2.c
index bc01e8ef992..ee9925b7498 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-and-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-and-2.c
@@ -38,5 +38,24 @@ sub6 (long i, long j)
{
return i << (j & 0x3f);
}
+
+/* Test for <optab>si3_extend. */
+int
+sub7 (int i, int j) {
+ return (i << 10) & j;
+}
+
+/* Test for <optab>si3_extend. */
+unsigned
+sub8 (unsigned i, unsigned j) {
+ return (i << 10) & j;
+}
+
+/* Test for <optab>si3_extend. */
+unsigned
+sub9 (unsigned i, unsigned j) {
+ return (i >> 10) & j;
+}
+
/* { dg-final { scan-assembler-not "andi" } } */
/* { dg-final { scan-assembler-not "sext.w" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
index 5f93be15ac5..bc8c4ef3828 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
@@ -38,5 +38,6 @@ sub5 (unsigned int i)
}
/* { dg-final { scan-assembler-times "slli" 5 } } */
/* { dg-final { scan-assembler-times "srli" 5 } } */
-/* { dg-final { scan-assembler-times "slliw" 1 } } */
-/* { dg-final { scan-assembler-times "srliw" 1 } } */
+/* { dg-final { scan-assembler-times ",40" 2 } } */ /* For sub5 test */
+/* { dg-final { scan-assembler-not "slliw" } } */
+/* { dg-final { scan-assembler-not "srliw" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend.c b/gcc/testsuite/gcc.target/riscv/sign-extend.c
new file mode 100644
index 00000000000..6f840194833
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend.c
@@ -0,0 +1,81 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+unsigned
+foo1 (unsigned x, unsigned y, unsigned z)
+{
+ return x & (y - z);
+}
+
+int
+foo2 (int x, int y, int z)
+{
+ return x & (y - z);
+}
+
+unsigned
+foo3 (unsigned x, unsigned y, unsigned z)
+{
+ return x & (y * z);
+}
+
+int
+foo4 (int x, int y, int z)
+{
+ return x & (y * z);
+}
+
+unsigned
+foo5 (unsigned x, unsigned y)
+{
+ return x & (y / x);
+}
+
+int
+foo6 (int x, int y)
+{
+ return x & (y / x);
+}
+
+unsigned
+foo7 (unsigned x, unsigned y)
+{
+ return x & (y % x);
+}
+
+int
+foo8 (int x, int y)
+{
+ return x & (y % x);
+}
+
+int
+foo9 (int x)
+{
+ return x & (-x);
+}
+
+unsigned
+foo10 (unsigned x, unsigned y)
+{
+ return x & (y + x);
+}
+
+
+unsigned
+foo11 (unsigned x)
+{
+ return x & (15 + x);
+}
+
+/* { dg-final { scan-assembler-times "subw" 2 } } */
+/* { dg-final { scan-assembler-times "addw" 1 } } */
+/* { dg-final { scan-assembler-times "addiw" 1 } } */
+/* { dg-final { scan-assembler-times "mulw" 2 } } */
+/* { dg-final { scan-assembler-times "divw" 1 } } */
+/* { dg-final { scan-assembler-times "divuw" 1 } } */
+/* { dg-final { scan-assembler-times "remw" 1 } } */
+/* { dg-final { scan-assembler-times "remuw" 1 } } */
+/* { dg-final { scan-assembler-times "negw" 1 } } */
+/* { dg-final { scan-assembler-not "sext.w" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
index e2b135f3d00..d0df59c5e1c 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
@@ -5,9 +5,9 @@
/*
**ConEmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,10
-** th.mvnez a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_imm_reg(int x, int y){
@@ -17,9 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){
/*
**ConEmv_imm_reg_reg:
-** addi a5,a0,-1000
-** th.mveqz a2,a1,a5
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_reg_reg(int x, int y, int z){
@@ -29,9 +29,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z){
/*
**ConEmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mvnez a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_imm_reg(int x, int y, int z){
@@ -41,9 +41,9 @@ int ConEmv_reg_imm_reg(int x, int y, int z){
/*
**ConEmv_reg_reg_reg:
-** sub a1,a0,a1
-** th.mveqz a3,a2,a1
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_reg_reg(int x, int y, int z, int n){
@@ -53,10 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){
/*
**ConNmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,9998336
-** addi a0,a0,1664
-** th.mveqz a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,9998336+
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_imm_reg(int x, int y){
@@ -66,9 +66,9 @@ int ConNmv_imm_imm_reg(int x, int y){
/*
**ConNmv_imm_reg_reg:
-** addi a0,a0,-1000
-** th.mvnez a2,a1,a0
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_reg_reg(int x, int y, int z){
@@ -78,9 +78,9 @@ int ConNmv_imm_reg_reg(int x, int y, int z){
/*
**ConNmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mveqz a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_imm_reg(int x, int y, int z){
@@ -90,9 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){
/*
**ConNmv_reg_reg_reg:
-** sub a0,a0,a1
-** th.mvnez a3,a2,a0
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_reg_reg(int x, int y, int z, int n){
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
index 99956f8496c..cc971a75ace 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
@@ -5,9 +5,9 @@
/*
**ConEmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,10
-** th.mvnez a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_imm_reg(int x, int y){
@@ -17,9 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){
/*
**ConEmv_imm_reg_reg:
-** addi a0,a0,-1000
-** th.mveqz a2,a1,a5
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_imm_reg_reg(int x, int y, int z){
@@ -29,9 +29,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z){
/*
**ConEmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mvnez a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_imm_reg(int x, int y, int z){
@@ -41,9 +41,9 @@ int ConEmv_reg_imm_reg(int x, int y, int z){
/*
**ConEmv_reg_reg_reg:
-** sub a1,a0,a1
-** th.mveqz a3,a2,a1
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConEmv_reg_reg_reg(int x, int y, int z, int n){
@@ -53,10 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){
/*
**ConNmv_imm_imm_reg:
-** addi a5,a0,-1000
-** li a0,9998336
-** addi a0,a0,1664
-** th.mveqz a0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,9998336+
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_imm_reg(int x, int y){
@@ -66,9 +66,9 @@ int ConNmv_imm_imm_reg(int x, int y){
/*
**ConNmv_imm_reg_reg:
-** addi a5,a0,-1000
-** th.mvnez a2,a1,a0
-** mv a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_imm_reg_reg(int x, int y, int z){
@@ -78,9 +78,9 @@ int ConNmv_imm_reg_reg(int x, int y, int z){
/*
**ConNmv_reg_imm_reg:
-** sub a1,a0,a1
-** li a0,10
-** th.mveqz a0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_imm_reg(int x, int y, int z){
@@ -90,9 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){
/*
**ConNmv_reg_reg_reg:
-** sub a0,a0,a1
-** th.mvnez a3,a2,a0
-** mv a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
** ret
*/
int ConNmv_reg_reg_reg(int x, int y, int z, int n){
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
index b44d7fe8920..e7e5cbb9a1a 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
@@ -16,4 +16,5 @@ unsigned int ror(unsigned int rs1, unsigned int rs2)
/* { dg-final { scan-assembler-times "rolw" 1 } } */
/* { dg-final { scan-assembler-times "rorw" 1 } } */
-/* { dg-final { scan-assembler-not "and" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "and" } } */
+/* { dg-final { scan-assembler-not "sext.w" } } */
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-07-14 2:43 UTC | newest]
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2023-06-05 16:18 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c Jeff Law
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2023-07-14 2:43 Jeff Law
2023-05-31 15:31 Jeff Law
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