[gcc r14-1717] RISC-V: Fix one potential test failure for RVV vsetvl

[gcc r14-1717] RISC-V: Fix one potential test failure for RVV vsetvl

[Pan Li]

https://gcc.gnu.org/g:7a4794af9aa2d7621b67ea026f29a771590f61a1

commit r14-1717-g7a4794af9aa2d7621b67ea026f29a771590f61a1
Author: Pan Li <pan2.li@intel.com>
Date:   Mon Jun 12 20:07:24 2023 +0800

    RISC-V: Fix one potential test failure for RVV vsetvl
    
    The test will fail on below command with multi-thread like below.  However,
    it comes from one missed "Oz" option when check vsetvl.
    
    make -j $(nproc) report RUNTESTFLAGS="rvv.exp riscv.exp"
    
    To some reason, this failure cannot be reproduced by RUNTESTFLAGS="rvv.exp"
    or make without -j option. We would like to fix it and root cause the
    reason later.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Adjust test checking.

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
index 66c90ac10e7..f3420be8ab6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
@@ -34,4 +34,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) {
 /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*8} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */