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From: Jeff Law <law@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one typo in full-vec-movel test Date: Mon, 19 Jun 2023 11:40:55 +0000 (GMT) [thread overview] Message-ID: <20230619114055.6213C385840D@sourceware.org> (raw) https://gcc.gnu.org/g:1e48e2ec2cd922f6c4a252c0367b67dfc08da47e commit 1e48e2ec2cd922f6c4a252c0367b67dfc08da47e Author: Pan Li <pan2.li@intel.com> Date: Tue Jun 13 15:13:48 2023 +0800 RISC-V: Fix one typo in full-vec-movel test This patch would like to fix one typo when checking assembly of full-vec-movel. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Adjust dg-do to comiple for asm checking. Diff: --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c index c1119cddee7..c32c31ecd69 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do compile } */ /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include <stdint-gcc.h>
next reply other threads:[~2023-06-19 11:40 UTC|newest] Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-06-19 11:40 Jeff Law [this message] 2023-07-14 2:45 Jeff Law
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