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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one typo in full-vec-movel test
@ 2023-06-19 11:40 Jeff Law
  0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-06-19 11:40 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:1e48e2ec2cd922f6c4a252c0367b67dfc08da47e

commit 1e48e2ec2cd922f6c4a252c0367b67dfc08da47e
Author: Pan Li <pan2.li@intel.com>
Date:   Tue Jun 13 15:13:48 2023 +0800

    RISC-V: Fix one typo in full-vec-movel test
    
    This patch would like to fix one typo when checking assembly of
    full-vec-movel.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
            Adjust dg-do to comiple for asm checking.

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index c1119cddee7..c32c31ecd69 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do compile } */
 /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include <stdint-gcc.h>

^ permalink raw reply	[flat|nested] 2+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one typo in full-vec-movel test
@ 2023-07-14  2:45 Jeff Law
  0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-07-14  2:45 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:792ffe336f14623e10002dedaf5cd0d80846404e

commit 792ffe336f14623e10002dedaf5cd0d80846404e
Author: Pan Li <pan2.li@intel.com>
Date:   Tue Jun 13 15:13:48 2023 +0800

    RISC-V: Fix one typo in full-vec-movel test
    
    This patch would like to fix one typo when checking assembly of
    full-vec-movel.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
            Adjust dg-do to comiple for asm checking.

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index c1119cddee7..c32c31ecd69 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do compile } */
 /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include <stdint-gcc.h>

^ permalink raw reply	[flat|nested] 2+ messages in thread
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2023-06-19 11:40 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one typo in full-vec-movel test Jeff Law
2023-07-14  2:45 Jeff Law

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