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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add vector psabi checking.
@ 2023-06-19 11:41 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-06-19 11:41 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bf8a43ad550d4fd7537371138158e47ee8509ca0
commit bf8a43ad550d4fd7537371138158e47ee8509ca0
Author: Yanzhang Wang <yanzhang.wang@intel.com>
Date: Tue Jun 13 10:46:40 2023 +0800
RISC-V: Add vector psabi checking.
This patch adds support to check function's argument or return is vector type
and throw warning if yes.
There're two exceptions,
- The vector_size attribute.
- The intrinsic functions.
Some cases that need to add -Wno-psabi to ignore the warning.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
warning flag if func is not builtin
* config/riscv/riscv.cc
(riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
(riscv_arg_has_vector): Determine whether the arg is vector type.
(riscv_pass_in_vector_p): Check the vector type param is passed by value.
(riscv_init_cumulative_args): The same as header.
(riscv_get_arg_info): Add the checking.
(riscv_function_value): Check the func return and set warning flag
* config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
determine whether warning psabi or not.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr109244.C: Add the -Wno-psabi.
* g++.target/riscv/rvv/base/pr109535.C: Same
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Same
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Same
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Same
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Same
* gcc.target/riscv/rvv/base/pr110109-2.c: Same
* gcc.target/riscv/rvv/base/scalar_move-9.c: Same
* gcc.target/riscv/rvv/base/spill-10.c: Same
* gcc.target/riscv/rvv/base/spill-11.c: Same
* gcc.target/riscv/rvv/base/spill-9.c: Same
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Same
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Same
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Same
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Same
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Same
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Same
* gcc.target/riscv/vector-abi-1.c: New test.
* gcc.target/riscv/vector-abi-2.c: New test.
* gcc.target/riscv/vector-abi-3.c: New test.
* gcc.target/riscv/vector-abi-4.c: New test.
* gcc.target/riscv/vector-abi-5.c: New test.
* gcc.target/riscv/vector-abi-6.c: New test.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Diff:
---
gcc/config/riscv/riscv-protos.h | 2 +
gcc/config/riscv/riscv.cc | 112 ++++++++++++++++++++-
gcc/config/riscv/riscv.h | 5 +-
gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C | 2 +-
gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C | 2 +-
.../riscv/rvv/base/binop_vx_constraint-120.c | 2 +-
.../riscv/rvv/base/integer_compare_insn_shortcut.c | 2 +-
.../gcc.target/riscv/rvv/base/mask_insn_shortcut.c | 2 +-
.../riscv/rvv/base/misc_vreinterpret_vbool_vint.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110109-2.c | 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +-
.../rvv/base/zero_base_load_store_optimization.c | 2 +-
.../gcc.target/riscv/rvv/base/zvfh-intrinsic.c | 2 +-
.../gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c | 2 +-
.../gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 +++
gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 15 +++
gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 +++
gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 +++
gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 +++
gcc/testsuite/gcc.target/riscv/vector-abi-6.c | 20 ++++
26 files changed, 228 insertions(+), 19 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 6db3a46c682..b23a9c12465 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -303,4 +303,6 @@ th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
#endif
extern bool riscv_use_divmod_expander (void);
+void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
+
#endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index de30bf4e567..dd5361c2bd2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3795,6 +3795,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2))));
}
+/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
+ intrinsic vector type. Because we can't get the decl for the params. */
+
+static bool
+riscv_scalable_vector_type_p (const_tree type)
+{
+ tree size = TYPE_SIZE (type);
+ if (size && TREE_CODE (size) == INTEGER_CST)
+ return false;
+
+ /* For the data type like vint32m1_t, the size code is POLY_INT_CST. */
+ return true;
+}
+
+static bool
+riscv_arg_has_vector (const_tree type)
+{
+ bool is_vector = false;
+
+ switch (TREE_CODE (type))
+ {
+ case RECORD_TYPE:
+ if (!COMPLETE_TYPE_P (type))
+ break;
+
+ for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
+ if (TREE_CODE (f) == FIELD_DECL)
+ {
+ tree field_type = TREE_TYPE (f);
+ if (!TYPE_P (field_type))
+ break;
+
+ /* Ignore it if it's fixed length vector. */
+ if (VECTOR_TYPE_P (field_type))
+ is_vector = riscv_scalable_vector_type_p (field_type);
+ else
+ is_vector = riscv_arg_has_vector (field_type);
+ }
+
+ break;
+
+ case VECTOR_TYPE:
+ is_vector = riscv_scalable_vector_type_p (type);
+ break;
+
+ default:
+ is_vector = false;
+ break;
+ }
+
+ return is_vector;
+}
+
+/* Pass the type to check whether it's a vector type or contains vector type.
+ Only check the value type and no checking for vector pointer type. */
+
+static void
+riscv_pass_in_vector_p (const_tree type)
+{
+ static int warned = 0;
+
+ if (type && riscv_arg_has_vector (type) && !warned)
+ {
+ warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
+ "experimental stage and may changes in the upcoming version of "
+ "GCC.");
+ warned = 1;
+ }
+}
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+ for a call to a function whose data type is FNTYPE.
+ For a library call, FNTYPE is 0. */
+
+void
+riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
+ tree fntype ATTRIBUTE_UNUSED,
+ rtx libname ATTRIBUTE_UNUSED,
+ tree fndecl,
+ int caller ATTRIBUTE_UNUSED)
+{
+ memset (cum, 0, sizeof (*cum));
+
+ if (fndecl)
+ {
+ const tree_function_decl &fn
+ = FUNCTION_DECL_CHECK (fndecl)->function_decl;
+
+ if (fn.built_in_class == NOT_BUILT_IN)
+ cum->rvv_psabi_warning = 1;
+ }
+}
+
/* Fill INFO with information about a single argument, and return an
RTL pattern to pass or return the argument. CUM is the cumulative
state for earlier arguments. MODE is the mode of this argument and
@@ -3816,6 +3909,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
info->gpr_offset = cum->num_gprs;
info->fpr_offset = cum->num_fprs;
+ if (cum->rvv_psabi_warning)
+ {
+ /* Only check existing of vector type. */
+ riscv_pass_in_vector_p (type);
+ }
+
/* TODO: Currently, it will cause an ICE for --param
riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here
let GCC generate loads/stores. Ideally, we should either warn the user not
@@ -3973,7 +4072,18 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
}
memset (&args, 0, sizeof args);
- return riscv_get_arg_info (&info, &args, mode, type, true, true);
+
+ const_tree arg_type = type;
+ if (func && DECL_RESULT (func))
+ {
+ const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
+ if (fn.built_in_class == NOT_BUILT_IN)
+ args.rvv_psabi_warning = 1;
+
+ arg_type = TREE_TYPE (DECL_RESULT (func));
+ }
+
+ return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
}
/* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4541255a8ae..bfd9b7551bc 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -677,6 +677,8 @@ typedef struct {
/* Number of floating-point registers used so far, likewise. */
unsigned int num_fprs;
+
+ int rvv_psabi_warning;
} CUMULATIVE_ARGS;
/* Initialize a variable CUM of type CUMULATIVE_ARGS
@@ -684,7 +686,8 @@ typedef struct {
For a library call, FNTYPE is 0. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
- memset (&(CUM), 0, sizeof (CUM))
+ riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), \
+ (N_NAMED_ARGS) != -1)
#define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
index eebfc239d3a..b0ce04f4921 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -Wno-psabi" } */
typedef int a;
using c = float;
template < typename > using e = int;
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
index 7013cfcf4ee..aec613f3f97 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -Wno-psabi" } */
typedef long size_t;
typedef signed char int8_t;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
index 809b185dd65..cc373465957 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, vint8mf8_t op1,int8_t op2,size_t vl)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
index 1bca8467a16..2942e0b2e53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index 57d0241675a..a6df1215c60 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index 9563c8d27fa..276173d02db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
index e8b5bf8c714..c1df69ace57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
index 80ee1b5f0c9..9c310bbf590 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index d37857e24ab..89c96c8ef5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index aa2e5e75330..179be1c8c5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index ec673575b4b..5464a297670 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
index 501d98c5897..51f4fac0a8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
index fbcfb7b8501..b27e5ccad09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index c951644de4b..0e7c7cdbdd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 1d82cc8de2d..9ae79663adf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 1026b3f82f1..fc70c54c7fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index b82e2490815..0e76f676515 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
new file mode 100644
index 00000000000..969f14277a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+ vint32m1_t a;
+ fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
new file mode 100644
index 00000000000..63d97d30fc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+fun (vint32m1_t* a) { return *a; } /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+ vint32m1_t a;
+ fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
new file mode 100644
index 00000000000..90ece60cc6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t*
+fun (vint32m1_t* a) { return a; } /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+ vint32m1_t a;
+ fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
new file mode 100644
index 00000000000..ecf6d4cc26b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) { return a; } /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+ v4si a;
+ fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
new file mode 100644
index 00000000000..6053e0783b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+struct A { int a; v4si b; };
+
+void
+fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+ struct A a;
+ fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
new file mode 100644
index 00000000000..63bc4a89805
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+#include "riscv_vector.h"
+
+void
+foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
+ size_t n, int cond) {
+ size_t vl;
+ if (cond)
+ vl = __riscv_vsetvlmax_e32m1();
+ else
+ vl = __riscv_vsetvlmax_e16mf2();
+ for (size_t i = 0; i < n; i += 1)
+ {
+ vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
+ vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+ vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+ __riscv_vse32_v_i32m1(out, c, vl);
+ }
+}
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add vector psabi checking.
@ 2023-07-14 2:45 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-07-14 2:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:318817e3fc731cc3746282b5de1b2de6022407ae
commit 318817e3fc731cc3746282b5de1b2de6022407ae
Author: Yanzhang Wang <yanzhang.wang@intel.com>
Date: Tue Jun 13 10:46:40 2023 +0800
RISC-V: Add vector psabi checking.
This patch adds support to check function's argument or return is vector type
and throw warning if yes.
There're two exceptions,
- The vector_size attribute.
- The intrinsic functions.
Some cases that need to add -Wno-psabi to ignore the warning.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
warning flag if func is not builtin
* config/riscv/riscv.cc
(riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
(riscv_arg_has_vector): Determine whether the arg is vector type.
(riscv_pass_in_vector_p): Check the vector type param is passed by value.
(riscv_init_cumulative_args): The same as header.
(riscv_get_arg_info): Add the checking.
(riscv_function_value): Check the func return and set warning flag
* config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
determine whether warning psabi or not.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr109244.C: Add the -Wno-psabi.
* g++.target/riscv/rvv/base/pr109535.C: Same
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Same
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Same
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Same
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Same
* gcc.target/riscv/rvv/base/pr110109-2.c: Same
* gcc.target/riscv/rvv/base/scalar_move-9.c: Same
* gcc.target/riscv/rvv/base/spill-10.c: Same
* gcc.target/riscv/rvv/base/spill-11.c: Same
* gcc.target/riscv/rvv/base/spill-9.c: Same
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Same
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Same
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Same
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Same
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Same
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Same
* gcc.target/riscv/vector-abi-1.c: New test.
* gcc.target/riscv/vector-abi-2.c: New test.
* gcc.target/riscv/vector-abi-3.c: New test.
* gcc.target/riscv/vector-abi-4.c: New test.
* gcc.target/riscv/vector-abi-5.c: New test.
* gcc.target/riscv/vector-abi-6.c: New test.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Diff:
---
gcc/config/riscv/riscv-protos.h | 2 +
gcc/config/riscv/riscv.cc | 112 ++++++++++++++++++++-
gcc/config/riscv/riscv.h | 5 +-
gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C | 2 +-
gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C | 2 +-
.../riscv/rvv/base/binop_vx_constraint-120.c | 2 +-
.../riscv/rvv/base/integer_compare_insn_shortcut.c | 2 +-
.../gcc.target/riscv/rvv/base/mask_insn_shortcut.c | 2 +-
.../riscv/rvv/base/misc_vreinterpret_vbool_vint.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110109-2.c | 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +-
.../rvv/base/zero_base_load_store_optimization.c | 2 +-
.../gcc.target/riscv/rvv/base/zvfh-intrinsic.c | 2 +-
.../gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c | 2 +-
.../gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 +++
gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 15 +++
gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 +++
gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 +++
gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 +++
gcc/testsuite/gcc.target/riscv/vector-abi-6.c | 20 ++++
26 files changed, 228 insertions(+), 19 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 6db3a46c682..b23a9c12465 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -303,4 +303,6 @@ th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
#endif
extern bool riscv_use_divmod_expander (void);
+void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
+
#endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index de30bf4e567..dd5361c2bd2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3795,6 +3795,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2))));
}
+/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
+ intrinsic vector type. Because we can't get the decl for the params. */
+
+static bool
+riscv_scalable_vector_type_p (const_tree type)
+{
+ tree size = TYPE_SIZE (type);
+ if (size && TREE_CODE (size) == INTEGER_CST)
+ return false;
+
+ /* For the data type like vint32m1_t, the size code is POLY_INT_CST. */
+ return true;
+}
+
+static bool
+riscv_arg_has_vector (const_tree type)
+{
+ bool is_vector = false;
+
+ switch (TREE_CODE (type))
+ {
+ case RECORD_TYPE:
+ if (!COMPLETE_TYPE_P (type))
+ break;
+
+ for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
+ if (TREE_CODE (f) == FIELD_DECL)
+ {
+ tree field_type = TREE_TYPE (f);
+ if (!TYPE_P (field_type))
+ break;
+
+ /* Ignore it if it's fixed length vector. */
+ if (VECTOR_TYPE_P (field_type))
+ is_vector = riscv_scalable_vector_type_p (field_type);
+ else
+ is_vector = riscv_arg_has_vector (field_type);
+ }
+
+ break;
+
+ case VECTOR_TYPE:
+ is_vector = riscv_scalable_vector_type_p (type);
+ break;
+
+ default:
+ is_vector = false;
+ break;
+ }
+
+ return is_vector;
+}
+
+/* Pass the type to check whether it's a vector type or contains vector type.
+ Only check the value type and no checking for vector pointer type. */
+
+static void
+riscv_pass_in_vector_p (const_tree type)
+{
+ static int warned = 0;
+
+ if (type && riscv_arg_has_vector (type) && !warned)
+ {
+ warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
+ "experimental stage and may changes in the upcoming version of "
+ "GCC.");
+ warned = 1;
+ }
+}
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+ for a call to a function whose data type is FNTYPE.
+ For a library call, FNTYPE is 0. */
+
+void
+riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
+ tree fntype ATTRIBUTE_UNUSED,
+ rtx libname ATTRIBUTE_UNUSED,
+ tree fndecl,
+ int caller ATTRIBUTE_UNUSED)
+{
+ memset (cum, 0, sizeof (*cum));
+
+ if (fndecl)
+ {
+ const tree_function_decl &fn
+ = FUNCTION_DECL_CHECK (fndecl)->function_decl;
+
+ if (fn.built_in_class == NOT_BUILT_IN)
+ cum->rvv_psabi_warning = 1;
+ }
+}
+
/* Fill INFO with information about a single argument, and return an
RTL pattern to pass or return the argument. CUM is the cumulative
state for earlier arguments. MODE is the mode of this argument and
@@ -3816,6 +3909,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
info->gpr_offset = cum->num_gprs;
info->fpr_offset = cum->num_fprs;
+ if (cum->rvv_psabi_warning)
+ {
+ /* Only check existing of vector type. */
+ riscv_pass_in_vector_p (type);
+ }
+
/* TODO: Currently, it will cause an ICE for --param
riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here
let GCC generate loads/stores. Ideally, we should either warn the user not
@@ -3973,7 +4072,18 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
}
memset (&args, 0, sizeof args);
- return riscv_get_arg_info (&info, &args, mode, type, true, true);
+
+ const_tree arg_type = type;
+ if (func && DECL_RESULT (func))
+ {
+ const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
+ if (fn.built_in_class == NOT_BUILT_IN)
+ args.rvv_psabi_warning = 1;
+
+ arg_type = TREE_TYPE (DECL_RESULT (func));
+ }
+
+ return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
}
/* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4541255a8ae..bfd9b7551bc 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -677,6 +677,8 @@ typedef struct {
/* Number of floating-point registers used so far, likewise. */
unsigned int num_fprs;
+
+ int rvv_psabi_warning;
} CUMULATIVE_ARGS;
/* Initialize a variable CUM of type CUMULATIVE_ARGS
@@ -684,7 +686,8 @@ typedef struct {
For a library call, FNTYPE is 0. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
- memset (&(CUM), 0, sizeof (CUM))
+ riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), \
+ (N_NAMED_ARGS) != -1)
#define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
index eebfc239d3a..b0ce04f4921 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -Wno-psabi" } */
typedef int a;
using c = float;
template < typename > using e = int;
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
index 7013cfcf4ee..aec613f3f97 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -Wno-psabi" } */
typedef long size_t;
typedef signed char int8_t;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
index 809b185dd65..cc373465957 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, vint8mf8_t op1,int8_t op2,size_t vl)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
index 1bca8467a16..2942e0b2e53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index 57d0241675a..a6df1215c60 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index 9563c8d27fa..276173d02db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
index e8b5bf8c714..c1df69ace57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
index 80ee1b5f0c9..9c310bbf590 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index d37857e24ab..89c96c8ef5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index aa2e5e75330..179be1c8c5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index ec673575b4b..5464a297670 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
index 501d98c5897..51f4fac0a8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
index fbcfb7b8501..b27e5ccad09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index c951644de4b..0e7c7cdbdd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 1d82cc8de2d..9ae79663adf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 1026b3f82f1..fc70c54c7fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index b82e2490815..0e76f676515 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
new file mode 100644
index 00000000000..969f14277a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+ vint32m1_t a;
+ fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
new file mode 100644
index 00000000000..63d97d30fc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+fun (vint32m1_t* a) { return *a; } /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+ vint32m1_t a;
+ fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
new file mode 100644
index 00000000000..90ece60cc6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t*
+fun (vint32m1_t* a) { return a; } /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+ vint32m1_t a;
+ fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
new file mode 100644
index 00000000000..ecf6d4cc26b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) { return a; } /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+ v4si a;
+ fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
new file mode 100644
index 00000000000..6053e0783b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+struct A { int a; v4si b; };
+
+void
+fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+ struct A a;
+ fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
new file mode 100644
index 00000000000..63bc4a89805
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+#include "riscv_vector.h"
+
+void
+foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
+ size_t n, int cond) {
+ size_t vl;
+ if (cond)
+ vl = __riscv_vsetvlmax_e32m1();
+ else
+ vl = __riscv_vsetvlmax_e16mf2();
+ for (size_t i = 0; i < n; i += 1)
+ {
+ vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
+ vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+ vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+ __riscv_vse32_v_i32m1(out, c, vl);
+ }
+}
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2023-06-19 11:41 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add vector psabi checking Jeff Law
2023-07-14 2:45 Jeff Law
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