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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add more SLP tests
@ 2023-06-19 11:41 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-06-19 11:41 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8c6f53d0ccc40f0eaadc495a10ed80d099cc6e78
commit 8c6f53d0ccc40f0eaadc495a10ed80d099cc6e78
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Tue Jun 13 19:38:38 2023 +0800
RISC-V: Add more SLP tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/partial/slp-10.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp-11.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp-13.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp-14.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp-15.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: New test.
Diff:
---
.../gcc.target/riscv/rvv/autovec/partial/slp-10.c | 32 ++++++++++++
.../gcc.target/riscv/rvv/autovec/partial/slp-11.c | 33 +++++++++++++
.../gcc.target/riscv/rvv/autovec/partial/slp-13.c | 34 +++++++++++++
.../gcc.target/riscv/rvv/autovec/partial/slp-14.c | 33 +++++++++++++
.../gcc.target/riscv/rvv/autovec/partial/slp-15.c | 35 +++++++++++++
.../riscv/rvv/autovec/partial/slp_run-10.c | 33 +++++++++++++
.../riscv/rvv/autovec/partial/slp_run-11.c | 33 +++++++++++++
.../riscv/rvv/autovec/partial/slp_run-13.c | 47 ++++++++++++++++++
.../riscv/rvv/autovec/partial/slp_run-14.c | 57 ++++++++++++++++++++++
.../riscv/rvv/autovec/partial/slp_run-15.c | 56 +++++++++++++++++++++
10 files changed, 393 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
new file mode 100644
index 00000000000..c5215611e53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i * 2] += 10; \
+ a[i * 2 + 1] += 17; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* { dg-final { scan-tree-dump-times "{ 10, 17, ... }" 8 "optimized" } } */
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
new file mode 100644
index 00000000000..ccb5ab6831d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i * 4] += 41; \
+ a[i * 4 + 1] += 25; \
+ a[i * 4 + 2] += 31; \
+ a[i * 4 + 3] += 62; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* { dg-final { scan-tree-dump "{ 41, 25, 31, 62, ... }" "optimized" } } */
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c
new file mode 100644
index 00000000000..807cb49a4c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ void __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, TYPE *restrict b, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i * 2] += 1; \
+ a[i * 2 + 1] += 2; \
+ b[i * 4] += 3; \
+ b[i * 4 + 1] += 4; \
+ b[i * 4 + 2] += 5; \
+ b[i * 4 + 3] += 6; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c
new file mode 100644
index 00000000000..e0d089e5434
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ void __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, TYPE *restrict b, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i] += 1; \
+ b[i * 4] += 2; \
+ b[i * 4 + 1] += 3; \
+ b[i * 4 + 2] += 4; \
+ b[i * 4 + 3] += 5; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c
new file mode 100644
index 00000000000..731b028b17a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define N1 (19 * 2)
+
+#define VEC_PERM(TYPE) \
+ void __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, TYPE *restrict b) \
+ { \
+ for (int i = 0; i < N1; ++i) \
+ { \
+ a[i] += 1; \
+ b[i * 4] += 2; \
+ b[i * 4 + 1] += 3; \
+ b[i * 4 + 2] += 4; \
+ b[i * 4 + 3] += 5; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
new file mode 100644
index 00000000000..be95309a463
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
@@ -0,0 +1,33 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-10.c"
+
+#define N (103 * 2)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N], b[2] = { 10, 17 }; \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ asm volatile ("" ::: "memory"); \
+ } \
+ vec_slp_##TYPE (a, N / 2); \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ TYPE orig = i * 2 + i % 5; \
+ TYPE expected = orig + b[i % 2]; \
+ if (a[i] != expected) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
new file mode 100644
index 00000000000..a48b18630e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
@@ -0,0 +1,33 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-11.c"
+
+#define N (77 * 4)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N], b[4] = { 41, 25, 31, 62 }; \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ asm volatile ("" ::: "memory"); \
+ } \
+ vec_slp_##TYPE (a, N / 4); \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ TYPE orig = i * 2 + i % 5; \
+ TYPE expected = orig + b[i % 4]; \
+ if (a[i] != expected) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c
new file mode 100644
index 00000000000..251054e4d6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-13.c"
+
+#define N1 (103 * 2)
+#define N2 (111 * 2)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N2], b[N2 * 2]; \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ b[i * 2] = i * 3 + i % 7; \
+ b[i * 2 + 1] = i * 5 + i % 9; \
+ } \
+ vec_slp_##TYPE (a, b, N1 / 2); \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ TYPE orig_a = i * 2 + i % 5; \
+ TYPE orig_b1 = i * 3 + i % 7; \
+ TYPE orig_b2 = i * 5 + i % 9; \
+ TYPE expected_a = orig_a; \
+ TYPE expected_b1 = orig_b1; \
+ TYPE expected_b2 = orig_b2; \
+ if (i < N1) \
+ { \
+ expected_a += i & 1 ? 2 : 1; \
+ expected_b1 += i & 1 ? 5 : 3; \
+ expected_b2 += i & 1 ? 6 : 4; \
+ } \
+ if (a[i] != expected_a \
+ || b[i * 2] != expected_b1 \
+ || b[i * 2 + 1] != expected_b2) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c
new file mode 100644
index 00000000000..d0f7f0b4f02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c
@@ -0,0 +1,57 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-14.c"
+
+#define N1 (103 * 2)
+#define N2 (111 * 2)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N2], b[N2 * 4]; \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ b[i * 4] = i * 3 + i % 7; \
+ b[i * 4 + 1] = i * 5 + i % 9; \
+ b[i * 4 + 2] = i * 7 + i % 11; \
+ b[i * 4 + 3] = i * 9 + i % 13; \
+ } \
+ vec_slp_##TYPE (a, b, N1); \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ TYPE orig_a = i * 2 + i % 5; \
+ TYPE orig_b1 = i * 3 + i % 7; \
+ TYPE orig_b2 = i * 5 + i % 9; \
+ TYPE orig_b3 = i * 7 + i % 11; \
+ TYPE orig_b4 = i * 9 + i % 13; \
+ TYPE expected_a = orig_a; \
+ TYPE expected_b1 = orig_b1; \
+ TYPE expected_b2 = orig_b2; \
+ TYPE expected_b3 = orig_b3; \
+ TYPE expected_b4 = orig_b4; \
+ if (i < N1) \
+ { \
+ expected_a += 1; \
+ expected_b1 += 2; \
+ expected_b2 += 3; \
+ expected_b3 += 4; \
+ expected_b4 += 5; \
+ } \
+ if (a[i] != expected_a \
+ || b[i * 4] != expected_b1 \
+ || b[i * 4 + 1] != expected_b2 \
+ || b[i * 4 + 2] != expected_b3 \
+ || b[i * 4 + 3] != expected_b4) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c
new file mode 100644
index 00000000000..df14f111ebe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c
@@ -0,0 +1,56 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-15.c"
+
+#define N2 (31 * 2)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N2], b[N2 * 4]; \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ b[i * 4] = i * 3 + i % 7; \
+ b[i * 4 + 1] = i * 5 + i % 9; \
+ b[i * 4 + 2] = i * 7 + i % 11; \
+ b[i * 4 + 3] = i * 9 + i % 13; \
+ } \
+ vec_slp_##TYPE (a, b); \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ TYPE orig_a = i * 2 + i % 5; \
+ TYPE orig_b1 = i * 3 + i % 7; \
+ TYPE orig_b2 = i * 5 + i % 9; \
+ TYPE orig_b3 = i * 7 + i % 11; \
+ TYPE orig_b4 = i * 9 + i % 13; \
+ TYPE expected_a = orig_a; \
+ TYPE expected_b1 = orig_b1; \
+ TYPE expected_b2 = orig_b2; \
+ TYPE expected_b3 = orig_b3; \
+ TYPE expected_b4 = orig_b4; \
+ if (i < N1) \
+ { \
+ expected_a += 1; \
+ expected_b1 += 2; \
+ expected_b2 += 3; \
+ expected_b3 += 4; \
+ expected_b4 += 5; \
+ } \
+ if (a[i] != expected_a \
+ || b[i * 4] != expected_b1 \
+ || b[i * 4 + 1] != expected_b2 \
+ || b[i * 4 + 2] != expected_b3 \
+ || b[i * 4 + 3] != expected_b4) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add more SLP tests
@ 2023-07-14 2:45 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-07-14 2:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b0998884c21cb0fef0430b631a6ec51fb9c0aeb8
commit b0998884c21cb0fef0430b631a6ec51fb9c0aeb8
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Tue Jun 13 19:38:38 2023 +0800
RISC-V: Add more SLP tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/partial/slp-10.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp-11.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp-13.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp-14.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp-15.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: New test.
Diff:
---
.../gcc.target/riscv/rvv/autovec/partial/slp-10.c | 32 ++++++++++++
.../gcc.target/riscv/rvv/autovec/partial/slp-11.c | 33 +++++++++++++
.../gcc.target/riscv/rvv/autovec/partial/slp-13.c | 34 +++++++++++++
.../gcc.target/riscv/rvv/autovec/partial/slp-14.c | 33 +++++++++++++
.../gcc.target/riscv/rvv/autovec/partial/slp-15.c | 35 +++++++++++++
.../riscv/rvv/autovec/partial/slp_run-10.c | 33 +++++++++++++
.../riscv/rvv/autovec/partial/slp_run-11.c | 33 +++++++++++++
.../riscv/rvv/autovec/partial/slp_run-13.c | 47 ++++++++++++++++++
.../riscv/rvv/autovec/partial/slp_run-14.c | 57 ++++++++++++++++++++++
.../riscv/rvv/autovec/partial/slp_run-15.c | 56 +++++++++++++++++++++
10 files changed, 393 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
new file mode 100644
index 00000000000..c5215611e53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i * 2] += 10; \
+ a[i * 2 + 1] += 17; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* { dg-final { scan-tree-dump-times "{ 10, 17, ... }" 8 "optimized" } } */
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
new file mode 100644
index 00000000000..ccb5ab6831d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i * 4] += 41; \
+ a[i * 4 + 1] += 25; \
+ a[i * 4 + 2] += 31; \
+ a[i * 4 + 3] += 62; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* { dg-final { scan-tree-dump "{ 41, 25, 31, 62, ... }" "optimized" } } */
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c
new file mode 100644
index 00000000000..807cb49a4c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ void __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, TYPE *restrict b, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i * 2] += 1; \
+ a[i * 2 + 1] += 2; \
+ b[i * 4] += 3; \
+ b[i * 4 + 1] += 4; \
+ b[i * 4 + 2] += 5; \
+ b[i * 4 + 3] += 6; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c
new file mode 100644
index 00000000000..e0d089e5434
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ void __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, TYPE *restrict b, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i] += 1; \
+ b[i * 4] += 2; \
+ b[i * 4 + 1] += 3; \
+ b[i * 4 + 2] += 4; \
+ b[i * 4 + 3] += 5; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c
new file mode 100644
index 00000000000..731b028b17a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define N1 (19 * 2)
+
+#define VEC_PERM(TYPE) \
+ void __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, TYPE *restrict b) \
+ { \
+ for (int i = 0; i < N1; ++i) \
+ { \
+ a[i] += 1; \
+ b[i * 4] += 2; \
+ b[i * 4 + 1] += 3; \
+ b[i * 4 + 2] += 4; \
+ b[i * 4 + 3] += 5; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
new file mode 100644
index 00000000000..be95309a463
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
@@ -0,0 +1,33 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-10.c"
+
+#define N (103 * 2)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N], b[2] = { 10, 17 }; \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ asm volatile ("" ::: "memory"); \
+ } \
+ vec_slp_##TYPE (a, N / 2); \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ TYPE orig = i * 2 + i % 5; \
+ TYPE expected = orig + b[i % 2]; \
+ if (a[i] != expected) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
new file mode 100644
index 00000000000..a48b18630e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
@@ -0,0 +1,33 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-11.c"
+
+#define N (77 * 4)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N], b[4] = { 41, 25, 31, 62 }; \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ asm volatile ("" ::: "memory"); \
+ } \
+ vec_slp_##TYPE (a, N / 4); \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ TYPE orig = i * 2 + i % 5; \
+ TYPE expected = orig + b[i % 4]; \
+ if (a[i] != expected) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c
new file mode 100644
index 00000000000..251054e4d6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-13.c"
+
+#define N1 (103 * 2)
+#define N2 (111 * 2)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N2], b[N2 * 2]; \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ b[i * 2] = i * 3 + i % 7; \
+ b[i * 2 + 1] = i * 5 + i % 9; \
+ } \
+ vec_slp_##TYPE (a, b, N1 / 2); \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ TYPE orig_a = i * 2 + i % 5; \
+ TYPE orig_b1 = i * 3 + i % 7; \
+ TYPE orig_b2 = i * 5 + i % 9; \
+ TYPE expected_a = orig_a; \
+ TYPE expected_b1 = orig_b1; \
+ TYPE expected_b2 = orig_b2; \
+ if (i < N1) \
+ { \
+ expected_a += i & 1 ? 2 : 1; \
+ expected_b1 += i & 1 ? 5 : 3; \
+ expected_b2 += i & 1 ? 6 : 4; \
+ } \
+ if (a[i] != expected_a \
+ || b[i * 2] != expected_b1 \
+ || b[i * 2 + 1] != expected_b2) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c
new file mode 100644
index 00000000000..d0f7f0b4f02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c
@@ -0,0 +1,57 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-14.c"
+
+#define N1 (103 * 2)
+#define N2 (111 * 2)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N2], b[N2 * 4]; \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ b[i * 4] = i * 3 + i % 7; \
+ b[i * 4 + 1] = i * 5 + i % 9; \
+ b[i * 4 + 2] = i * 7 + i % 11; \
+ b[i * 4 + 3] = i * 9 + i % 13; \
+ } \
+ vec_slp_##TYPE (a, b, N1); \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ TYPE orig_a = i * 2 + i % 5; \
+ TYPE orig_b1 = i * 3 + i % 7; \
+ TYPE orig_b2 = i * 5 + i % 9; \
+ TYPE orig_b3 = i * 7 + i % 11; \
+ TYPE orig_b4 = i * 9 + i % 13; \
+ TYPE expected_a = orig_a; \
+ TYPE expected_b1 = orig_b1; \
+ TYPE expected_b2 = orig_b2; \
+ TYPE expected_b3 = orig_b3; \
+ TYPE expected_b4 = orig_b4; \
+ if (i < N1) \
+ { \
+ expected_a += 1; \
+ expected_b1 += 2; \
+ expected_b2 += 3; \
+ expected_b3 += 4; \
+ expected_b4 += 5; \
+ } \
+ if (a[i] != expected_a \
+ || b[i * 4] != expected_b1 \
+ || b[i * 4 + 1] != expected_b2 \
+ || b[i * 4 + 2] != expected_b3 \
+ || b[i * 4 + 3] != expected_b4) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c
new file mode 100644
index 00000000000..df14f111ebe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c
@@ -0,0 +1,56 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-15.c"
+
+#define N2 (31 * 2)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N2], b[N2 * 4]; \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ b[i * 4] = i * 3 + i % 7; \
+ b[i * 4 + 1] = i * 5 + i % 9; \
+ b[i * 4 + 2] = i * 7 + i % 11; \
+ b[i * 4 + 3] = i * 9 + i % 13; \
+ } \
+ vec_slp_##TYPE (a, b); \
+ for (unsigned int i = 0; i < N2; ++i) \
+ { \
+ TYPE orig_a = i * 2 + i % 5; \
+ TYPE orig_b1 = i * 3 + i % 7; \
+ TYPE orig_b2 = i * 5 + i % 9; \
+ TYPE orig_b3 = i * 7 + i % 11; \
+ TYPE orig_b4 = i * 9 + i % 13; \
+ TYPE expected_a = orig_a; \
+ TYPE expected_b1 = orig_b1; \
+ TYPE expected_b2 = orig_b2; \
+ TYPE expected_b3 = orig_b3; \
+ TYPE expected_b4 = orig_b4; \
+ if (i < N1) \
+ { \
+ expected_a += 1; \
+ expected_b1 += 2; \
+ expected_b2 += 3; \
+ expected_b3 += 4; \
+ expected_b4 += 5; \
+ } \
+ if (a[i] != expected_a \
+ || b[i * 4] != expected_b1 \
+ || b[i * 4 + 1] != expected_b2 \
+ || b[i * 4 + 2] != expected_b3 \
+ || b[i * 4 + 3] != expected_b4) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
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2023-06-19 11:41 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add more SLP tests Jeff Law
2023-07-14 2:45 Jeff Law
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