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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one typo for reduc expand GET_MODE_CLASS
@ 2023-06-19 11:42 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-06-19 11:42 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e9881a11f613df99afca4140327a367f51b515e4
commit e9881a11f613df99afca4140327a367f51b515e4
Author: Pan Li <pan2.li@intel.com>
Date: Mon Jun 19 07:36:41 2023 +0800
RISC-V: Fix one typo for reduc expand GET_MODE_CLASS
This patch would like to fix one typo when GET_MODE_CLASS by mode.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Fix one typo.
Diff:
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 53bd0ed2534..b11b544291a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1400,7 +1400,7 @@ public:
machine_mode ret_mode = e.ret_mode ();
/* TODO: we will use ret_mode after all types of PR110265 are addressed. */
- if ((GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT)
+ if ((GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
|| GET_MODE_INNER (mode) != GET_MODE_INNER (ret_mode))
return e.use_exact_insn (
code_for_pred_reduc (CODE, e.vector_mode (), e.vector_mode ()));
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one typo for reduc expand GET_MODE_CLASS
@ 2023-07-14 2:46 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-07-14 2:46 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:fc5496943f6fd99cce6acbdd7e27192923749126
commit fc5496943f6fd99cce6acbdd7e27192923749126
Author: Pan Li <pan2.li@intel.com>
Date: Mon Jun 19 07:36:41 2023 +0800
RISC-V: Fix one typo for reduc expand GET_MODE_CLASS
This patch would like to fix one typo when GET_MODE_CLASS by mode.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Fix one typo.
Diff:
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 53bd0ed2534..b11b544291a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1400,7 +1400,7 @@ public:
machine_mode ret_mode = e.ret_mode ();
/* TODO: we will use ret_mode after all types of PR110265 are addressed. */
- if ((GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT)
+ if ((GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
|| GET_MODE_INNER (mode) != GET_MODE_INNER (ret_mode))
return e.use_exact_insn (
code_for_pred_reduc (CODE, e.vector_mode (), e.vector_mode ()));
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-06-19 11:42 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one typo for reduc expand GET_MODE_CLASS Jeff Law
2023-07-14 2:46 Jeff Law
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