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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add (u)int8_t to binop tests.
@ 2023-06-19 11:42 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-06-19 11:42 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:30af1e21e29fb985311f3aa8839ddd44e96f08b2
commit 30af1e21e29fb985311f3aa8839ddd44e96f08b2
Author: Robin Dapp <rdapp@ventanamicro.com>
Date: Mon Jun 5 10:44:22 2023 +0200
RISC-V: Add (u)int8_t to binop tests.
This patch adds the missing (u)int8_t types to the binop tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/shift-run.c: Adapt for
(u)int8_t.
* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/shift-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vadd-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vand-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmax-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmin-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmul-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vor-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vxor-template.h: Dito.
Diff:
---
.../gcc.target/riscv/rvv/autovec/binop/shift-run.c | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c | 10 +++-------
.../gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/binop/shift-template.h | 5 ++++-
.../gcc.target/riscv/rvv/autovec/binop/vadd-run.c | 6 ++++++
.../gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vadd-template.h | 7 ++++++-
.../gcc.target/riscv/rvv/autovec/binop/vand-run.c | 6 ++++++
.../gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vand-template.h | 7 ++++++-
.../gcc.target/riscv/rvv/autovec/binop/vdiv-run.c | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/binop/vdiv-template.h | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/vmax-run.c | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vmax-template.h | 5 ++++-
.../gcc.target/riscv/rvv/autovec/binop/vmin-run.c | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vmin-template.h | 5 ++++-
.../gcc.target/riscv/rvv/autovec/binop/vmul-run.c | 8 ++++++--
.../gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vmul-template.h | 9 ++++++---
.../gcc.target/riscv/rvv/autovec/binop/vor-run.c | 6 ++++++
.../gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vor-template.h | 7 ++++++-
.../gcc.target/riscv/rvv/autovec/binop/vrem-run.c | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/binop/vrem-template.h | 5 ++++-
.../gcc.target/riscv/rvv/autovec/binop/vsub-run.c | 16 ++++++++++++----
.../gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vsub-template.h | 12 +++++++++++-
.../gcc.target/riscv/rvv/autovec/binop/vxor-run.c | 6 ++++++
.../gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vxor-template.h | 7 ++++++-
44 files changed, 171 insertions(+), 70 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
index ff3633b530a..d7052b2270c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
@@ -32,12 +32,16 @@
assert (as##TYPE[i] == (VAL >> (i % 4)));
#define RUN_ALL() \
+ RUN(int8_t, 1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, 1) \
RUN(uint16_t, 2) \
RUN(int32_t, 3) \
RUN(uint32_t, 4) \
RUN(int64_t, 5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
index 557a7c82531..befa4b85e8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
@@ -3,10 +3,6 @@
#include "shift-template.h"
-/* TODO: For int16_t and uint16_t we need widening/promotion patterns.
- We don't check the assembler number since lacking patterns make
- auto-vectorization inconsistent in LMUL = 1/2/4/8. */
-
-/* { dg-final { scan-assembler {\tvsll\.vv} } } */
-/* { dg-final { scan-assembler {\tvsrl\.vv} } } */
-/* { dg-final { scan-assembler {\tvsra\.vv} } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
index 01a9cb21efc..976b29fa356 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
@@ -3,6 +3,6 @@
#include "shift-template.h"
-/* { dg-final { scan-assembler-times {\tvsll\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
index 16ae48c8ede..ca1b96f9f25 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
@@ -16,14 +16,17 @@
dst[i] = a[i] >> b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST1_TYPE(int8_t) \
+ TEST1_TYPE(uint8_t) \
TEST1_TYPE(int16_t) \
TEST1_TYPE(uint16_t) \
TEST1_TYPE(int32_t) \
TEST1_TYPE(uint32_t) \
TEST1_TYPE(int64_t) \
TEST1_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
index 8bdc7a220c3..4f6c8e773c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
@@ -44,18 +44,24 @@
assert (aim##TYPE[i] == VAL - 16);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
RUN2(uint32_t, 10) \
RUN2(int64_t, -11) \
RUN2(uint64_t, 12) \
+ RUN3M(int8_t, 13) \
+ RUN3(uint8_t, 14) \
RUN3M(int16_t, 13) \
RUN3(uint16_t, 14) \
RUN3M(int32_t, 15) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
index 799ed27ec6d..2d094749c6a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vadd-template.h"
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
index 64c2eeec7cf..4a1dc41c34a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vadd-template.h"
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
index cd945d471d2..fecf2947691 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
@@ -32,20 +32,25 @@
dst[i] = a[i] - 16; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
TEST2_TYPE(uint32_t) \
TEST2_TYPE(int64_t) \
TEST2_TYPE(uint64_t) \
+ TEST3M_TYPE(int8_t) \
+ TEST3_TYPE(uint8_t) \
TEST3M_TYPE(int16_t) \
TEST3_TYPE(uint16_t) \
TEST3M_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
index c13755ed06a..3fa6cf35e18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
@@ -44,18 +44,24 @@
assert (aim##TYPE[i] == (VAL & -16));
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
RUN2(uint32_t, 10) \
RUN2(int64_t, -11) \
RUN2(uint64_t, 12) \
+ RUN3M(int8_t, 13) \
+ RUN3(uint8_t, 14) \
RUN3M(int16_t, 13) \
RUN3(uint16_t, 14) \
RUN3M(int32_t, 15) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
index 24fc70b4ea4..f7636abdec0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vand-template.h"
-/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
index 67f37c1e170..dee8a2d6124 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vand-template.h"
-/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
index 5cabe073097..e2409594f39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
@@ -32,20 +32,25 @@
dst[i] = a[i] & -16; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
TEST2_TYPE(uint32_t) \
TEST2_TYPE(int64_t) \
TEST2_TYPE(uint64_t) \
+ TEST3M_TYPE(int8_t) \
+ TEST3_TYPE(uint8_t) \
TEST3M_TYPE(int16_t) \
TEST3_TYPE(uint16_t) \
TEST3M_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
index 5de339172fc..c4fd81f4bf2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
@@ -28,12 +28,16 @@
assert (as##TYPE[i] == 5);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
index 1dce9dd562e..9f059ebc84c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
@@ -4,7 +4,7 @@
#include "vdiv-template.h"
/* Currently we use an epilogue loop which also contains vdivs. Therefore we
- expect 10 vdiv[u]s instead of 6. */
+ expect 14 vdiv[u]s instead of 8. */
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
index 16a18c466e0..cd5d30b8974 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
@@ -4,7 +4,7 @@
#include "vdiv-template.h"
/* Currently we use an epilogue loop which also contains vdivs. Therefore we
- expect 10 vdiv[u]s instead of 6. */
+ expect 14 vdiv[u]s instead of 8. */
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
index f8d3bfde4ed..fd9199722b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
@@ -17,12 +17,16 @@
}
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
index cf184e24b1e..668f848694b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
@@ -28,12 +28,16 @@
assert (as##TYPE[i] == 0 > VAL ? 0 : VAL);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
index 46a321289fc..7b217d990a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vmax-template.h"
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
index 9bbaf763157..1b7f8c6be16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vmax-template.h"
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
index fc6a07e3ce9..6deb5126c7d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
@@ -16,14 +16,17 @@
dst[i] = a[i] > b ? a[i] : b; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
index b461f8ba484..63c05a119a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
@@ -28,12 +28,16 @@
assert (as##TYPE[i] == 0 < VAL ? 0 : VAL);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
index da3bb179ba7..bf826ebf53a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vmin-template.h"
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
index 07278b22b2d..f57d4369006 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vmin-template.h"
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
index 06f6b95461e..1225d5aca64 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
@@ -16,14 +16,17 @@
dst[i] = a[i] < b ? a[i] : b; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
index e8441c0605b..c560af9b85d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
@@ -15,7 +15,7 @@
a##TYPE[i] = 2; \
b##TYPE[i] = VAL; \
} \
- vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+ vmul_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
for (int i = 0; i < SZ; i++) \
assert (a##TYPE[i] == 2 * VAL);
@@ -23,17 +23,21 @@
TYPE as##TYPE[SZ]; \
for (int i = 0; i < SZ; i++) \
as##TYPE[i] = 3; \
- vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \
+ vmuls_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \
for (int i = 0; i < SZ; i++) \
assert (as##TYPE[i] == 3 * VAL);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
index f4df04d15eb..53d920010da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
@@ -3,4 +3,4 @@
#include "vmul-template.h"
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
index f436b8a82a8..1624e16a53c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
@@ -3,4 +3,4 @@
#include "vmul-template.h"
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
index 37f77972101..33f9d87e1bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
@@ -2,7 +2,7 @@
#define TEST_TYPE(TYPE) \
__attribute__((noipa)) \
- void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ void vmul_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
{ \
for (int i = 0; i < n; i++) \
dst[i] = a[i] * b[i]; \
@@ -10,20 +10,23 @@
#define TEST2_TYPE(TYPE) \
__attribute__((noipa)) \
- void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \
+ void vmuls_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \
{ \
for (int i = 0; i < n; i++) \
dst[i] = a[i] * b; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
index 5401e8d3ecd..f6b3770dcbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
@@ -44,18 +44,24 @@
assert (aim##TYPE[i] == (VAL | -16));
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
RUN2(uint32_t, 10) \
RUN2(int64_t, -11) \
RUN2(uint64_t, 12) \
+ RUN3M(int8_t, 13) \
+ RUN3(uint8_t, 14) \
RUN3M(int16_t, 13) \
RUN3(uint16_t, 14) \
RUN3M(int32_t, 15) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
index fc76d1c3b3e..70ea8ef65cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vor-template.h"
-/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
index ae115a2f503..44d09a2bddc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vor-template.h"
-/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
index e60146cc232..3daad2e8890 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
@@ -32,20 +32,25 @@
dst[i] = a[i] | -16; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
TEST2_TYPE(uint32_t) \
TEST2_TYPE(int64_t) \
TEST2_TYPE(uint64_t) \
+ TEST3M_TYPE(int8_t) \
+ TEST3_TYPE(uint8_t) \
TEST3M_TYPE(int16_t) \
TEST3_TYPE(uint16_t) \
TEST3M_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
index 4a4c064e101..58b69ec393e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
@@ -28,12 +28,16 @@
assert (as##TYPE[i] == 89 % VAL);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
index df99f5019fb..7d2b478e1de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
@@ -4,7 +4,7 @@
#include "vrem-template.h"
/* Currently we use an epilogue loop which also contains vrems. Therefore we
- expect 10 vrem[u]s instead of 6. */
+ expect 14 vrem[u]s instead of 8. */
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
index 3cff13a47e4..b7bc1ccb860 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
@@ -4,7 +4,7 @@
#include "vrem-template.h"
/* Currently we use an epilogue loop which also contains vrems. Therefore we
- expect 10 vrem[u]s instead of 6. */
+ expect 14 vrem[u]s instead of 8. */
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
index d5ef40667ff..9c4e6acae99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
@@ -16,14 +16,17 @@
dst[i] = a[i] % b; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
index 4f254872e33..fb6df757c90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
@@ -12,20 +12,20 @@
TYPE b##TYPE[SZ]; \
for (int i = 0; i < SZ; i++) \
{ \
- a##TYPE[i] = 999; \
+ a##TYPE[i] = 123; \
b##TYPE[i] = VAL; \
} \
vsub_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
for (int i = 0; i < SZ; i++) \
- assert (a##TYPE[i] == 999 - VAL);
+ assert (a##TYPE[i] == 123 - VAL);
#define RUN2(TYPE,VAL) \
TYPE as##TYPE[SZ]; \
for (int i = 0; i < SZ; i++) \
- as##TYPE[i] = 999; \
+ as##TYPE[i] = 123; \
vsubs_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \
for (int i = 0; i < SZ; i++) \
- assert (as##TYPE[i] == 999 - VAL);
+ assert (as##TYPE[i] == 123 - VAL);
#define RUN3(TYPE) \
TYPE as2##TYPE[SZ]; \
@@ -44,24 +44,32 @@
assert (as3##TYPE[i] == (TYPE)(15 - (i * -17 + 667)));
#define RUN_ALL() \
+ RUN(int8_t, 1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, 1) \
RUN(uint16_t, 2) \
RUN(int32_t, 3) \
RUN(uint32_t, 4) \
RUN(int64_t, 5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, 7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, 7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, 9) \
RUN2(uint32_t, 10) \
RUN2(int64_t, 11) \
RUN2(uint64_t, 12) \
+ RUN3(int8_t) \
+ RUN3(uint8_t) \
RUN3(int16_t) \
RUN3(uint16_t) \
RUN3(int32_t) \
RUN3(uint32_t) \
RUN3(int64_t) \
RUN3(uint64_t) \
+ RUN4(int8_t) \
+ RUN4(uint8_t) \
RUN4(int16_t) \
RUN4(uint16_t) \
RUN4(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
index a0d3802be65..5641432410e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vsub-template.h"
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
index 562c026a7e4..4fe0969c3a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vsub-template.h"
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
index 47f07f13462..222972d4752 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
@@ -32,26 +32,36 @@
dst[i] = 15 - a[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
TEST2_TYPE(uint32_t) \
TEST2_TYPE(int64_t) \
TEST2_TYPE(uint64_t)
+
+ TEST3_TYPE(int8_t) \
+ TEST3_TYPE(uint8_t) \
TEST3_TYPE(int16_t) \
TEST3_TYPE(uint16_t) \
TEST3_TYPE(int32_t) \
TEST3_TYPE(uint32_t) \
TEST3_TYPE(int64_t) \
TEST3_TYPE(uint64_t) \
+
+ TEST4_TYPE(int8_t) \
+ TEST4_TYPE(uint8_t) \
TEST4_TYPE(int16_t) \
TEST4_TYPE(uint16_t) \
TEST4_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
index ab0975a6408..7239733d12c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
@@ -44,18 +44,24 @@
assert (aim##TYPE[i] == (VAL ^ -16));
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
RUN2(uint32_t, 10) \
RUN2(int64_t, -11) \
RUN2(uint64_t, 12) \
+ RUN3M(int8_t, 13) \
+ RUN3(uint8_t, 14) \
RUN3M(int16_t, 13) \
RUN3(uint16_t, 14) \
RUN3M(int32_t, 15) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
index fbef4a45770..83b223e987f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vxor-template.h"
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
index 9729ad14eb1..6ba007c9d90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vxor-template.h"
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
index 370b242f197..b36698b5311 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
@@ -32,20 +32,25 @@
dst[i] = a[i] ^ -16; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
TEST2_TYPE(uint32_t) \
TEST2_TYPE(int64_t) \
TEST2_TYPE(uint64_t) \
+ TEST3M_TYPE(int8_t) \
+ TEST3_TYPE(uint8_t) \
TEST3M_TYPE(int16_t) \
TEST3_TYPE(uint16_t) \
TEST3M_TYPE(int32_t) \
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add (u)int8_t to binop tests.
@ 2023-07-14 2:46 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-07-14 2:46 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:16ef4d094a4cdb792889a8df79fa1246fe595513
commit 16ef4d094a4cdb792889a8df79fa1246fe595513
Author: Robin Dapp <rdapp@ventanamicro.com>
Date: Mon Jun 5 10:44:22 2023 +0200
RISC-V: Add (u)int8_t to binop tests.
This patch adds the missing (u)int8_t types to the binop tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/shift-run.c: Adapt for
(u)int8_t.
* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/shift-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vadd-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vand-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmax-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmin-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vmul-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vor-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vrem-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Dito.
* gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Dito.
* gcc.target/riscv/rvv/autovec/binop/vxor-template.h: Dito.
Diff:
---
.../gcc.target/riscv/rvv/autovec/binop/shift-run.c | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c | 10 +++-------
.../gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/binop/shift-template.h | 5 ++++-
.../gcc.target/riscv/rvv/autovec/binop/vadd-run.c | 6 ++++++
.../gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vadd-template.h | 7 ++++++-
.../gcc.target/riscv/rvv/autovec/binop/vand-run.c | 6 ++++++
.../gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vand-template.h | 7 ++++++-
.../gcc.target/riscv/rvv/autovec/binop/vdiv-run.c | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/binop/vdiv-template.h | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/vmax-run.c | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vmax-template.h | 5 ++++-
.../gcc.target/riscv/rvv/autovec/binop/vmin-run.c | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vmin-template.h | 5 ++++-
.../gcc.target/riscv/rvv/autovec/binop/vmul-run.c | 8 ++++++--
.../gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vmul-template.h | 9 ++++++---
.../gcc.target/riscv/rvv/autovec/binop/vor-run.c | 6 ++++++
.../gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vor-template.h | 7 ++++++-
.../gcc.target/riscv/rvv/autovec/binop/vrem-run.c | 4 ++++
.../gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/binop/vrem-template.h | 5 ++++-
.../gcc.target/riscv/rvv/autovec/binop/vsub-run.c | 16 ++++++++++++----
.../gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vsub-template.h | 12 +++++++++++-
.../gcc.target/riscv/rvv/autovec/binop/vxor-run.c | 6 ++++++
.../gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/binop/vxor-template.h | 7 ++++++-
44 files changed, 171 insertions(+), 70 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
index ff3633b530a..d7052b2270c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
@@ -32,12 +32,16 @@
assert (as##TYPE[i] == (VAL >> (i % 4)));
#define RUN_ALL() \
+ RUN(int8_t, 1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, 1) \
RUN(uint16_t, 2) \
RUN(int32_t, 3) \
RUN(uint32_t, 4) \
RUN(int64_t, 5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
index 557a7c82531..befa4b85e8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
@@ -3,10 +3,6 @@
#include "shift-template.h"
-/* TODO: For int16_t and uint16_t we need widening/promotion patterns.
- We don't check the assembler number since lacking patterns make
- auto-vectorization inconsistent in LMUL = 1/2/4/8. */
-
-/* { dg-final { scan-assembler {\tvsll\.vv} } } */
-/* { dg-final { scan-assembler {\tvsrl\.vv} } } */
-/* { dg-final { scan-assembler {\tvsra\.vv} } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
index 01a9cb21efc..976b29fa356 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
@@ -3,6 +3,6 @@
#include "shift-template.h"
-/* { dg-final { scan-assembler-times {\tvsll\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
index 16ae48c8ede..ca1b96f9f25 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
@@ -16,14 +16,17 @@
dst[i] = a[i] >> b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST1_TYPE(int8_t) \
+ TEST1_TYPE(uint8_t) \
TEST1_TYPE(int16_t) \
TEST1_TYPE(uint16_t) \
TEST1_TYPE(int32_t) \
TEST1_TYPE(uint32_t) \
TEST1_TYPE(int64_t) \
TEST1_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
index 8bdc7a220c3..4f6c8e773c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
@@ -44,18 +44,24 @@
assert (aim##TYPE[i] == VAL - 16);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
RUN2(uint32_t, 10) \
RUN2(int64_t, -11) \
RUN2(uint64_t, 12) \
+ RUN3M(int8_t, 13) \
+ RUN3(uint8_t, 14) \
RUN3M(int16_t, 13) \
RUN3(uint16_t, 14) \
RUN3M(int32_t, 15) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
index 799ed27ec6d..2d094749c6a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vadd-template.h"
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
index 64c2eeec7cf..4a1dc41c34a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vadd-template.h"
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
index cd945d471d2..fecf2947691 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
@@ -32,20 +32,25 @@
dst[i] = a[i] - 16; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
TEST2_TYPE(uint32_t) \
TEST2_TYPE(int64_t) \
TEST2_TYPE(uint64_t) \
+ TEST3M_TYPE(int8_t) \
+ TEST3_TYPE(uint8_t) \
TEST3M_TYPE(int16_t) \
TEST3_TYPE(uint16_t) \
TEST3M_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
index c13755ed06a..3fa6cf35e18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
@@ -44,18 +44,24 @@
assert (aim##TYPE[i] == (VAL & -16));
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
RUN2(uint32_t, 10) \
RUN2(int64_t, -11) \
RUN2(uint64_t, 12) \
+ RUN3M(int8_t, 13) \
+ RUN3(uint8_t, 14) \
RUN3M(int16_t, 13) \
RUN3(uint16_t, 14) \
RUN3M(int32_t, 15) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
index 24fc70b4ea4..f7636abdec0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vand-template.h"
-/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
index 67f37c1e170..dee8a2d6124 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vand-template.h"
-/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
index 5cabe073097..e2409594f39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
@@ -32,20 +32,25 @@
dst[i] = a[i] & -16; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
TEST2_TYPE(uint32_t) \
TEST2_TYPE(int64_t) \
TEST2_TYPE(uint64_t) \
+ TEST3M_TYPE(int8_t) \
+ TEST3_TYPE(uint8_t) \
TEST3M_TYPE(int16_t) \
TEST3_TYPE(uint16_t) \
TEST3M_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
index 5de339172fc..c4fd81f4bf2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
@@ -28,12 +28,16 @@
assert (as##TYPE[i] == 5);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
index 1dce9dd562e..9f059ebc84c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
@@ -4,7 +4,7 @@
#include "vdiv-template.h"
/* Currently we use an epilogue loop which also contains vdivs. Therefore we
- expect 10 vdiv[u]s instead of 6. */
+ expect 14 vdiv[u]s instead of 8. */
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
index 16a18c466e0..cd5d30b8974 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
@@ -4,7 +4,7 @@
#include "vdiv-template.h"
/* Currently we use an epilogue loop which also contains vdivs. Therefore we
- expect 10 vdiv[u]s instead of 6. */
+ expect 14 vdiv[u]s instead of 8. */
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
index f8d3bfde4ed..fd9199722b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
@@ -17,12 +17,16 @@
}
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
index cf184e24b1e..668f848694b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
@@ -28,12 +28,16 @@
assert (as##TYPE[i] == 0 > VAL ? 0 : VAL);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
index 46a321289fc..7b217d990a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vmax-template.h"
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
index 9bbaf763157..1b7f8c6be16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vmax-template.h"
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
index fc6a07e3ce9..6deb5126c7d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
@@ -16,14 +16,17 @@
dst[i] = a[i] > b ? a[i] : b; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
index b461f8ba484..63c05a119a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
@@ -28,12 +28,16 @@
assert (as##TYPE[i] == 0 < VAL ? 0 : VAL);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
index da3bb179ba7..bf826ebf53a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vmin-template.h"
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
index 07278b22b2d..f57d4369006 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vmin-template.h"
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
index 06f6b95461e..1225d5aca64 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
@@ -16,14 +16,17 @@
dst[i] = a[i] < b ? a[i] : b; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
index e8441c0605b..c560af9b85d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
@@ -15,7 +15,7 @@
a##TYPE[i] = 2; \
b##TYPE[i] = VAL; \
} \
- vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+ vmul_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
for (int i = 0; i < SZ; i++) \
assert (a##TYPE[i] == 2 * VAL);
@@ -23,17 +23,21 @@
TYPE as##TYPE[SZ]; \
for (int i = 0; i < SZ; i++) \
as##TYPE[i] = 3; \
- vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \
+ vmuls_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \
for (int i = 0; i < SZ; i++) \
assert (as##TYPE[i] == 3 * VAL);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
index f4df04d15eb..53d920010da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
@@ -3,4 +3,4 @@
#include "vmul-template.h"
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
index f436b8a82a8..1624e16a53c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
@@ -3,4 +3,4 @@
#include "vmul-template.h"
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
index 37f77972101..33f9d87e1bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
@@ -2,7 +2,7 @@
#define TEST_TYPE(TYPE) \
__attribute__((noipa)) \
- void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ void vmul_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
{ \
for (int i = 0; i < n; i++) \
dst[i] = a[i] * b[i]; \
@@ -10,20 +10,23 @@
#define TEST2_TYPE(TYPE) \
__attribute__((noipa)) \
- void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \
+ void vmuls_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \
{ \
for (int i = 0; i < n; i++) \
dst[i] = a[i] * b; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
index 5401e8d3ecd..f6b3770dcbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
@@ -44,18 +44,24 @@
assert (aim##TYPE[i] == (VAL | -16));
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
RUN2(uint32_t, 10) \
RUN2(int64_t, -11) \
RUN2(uint64_t, 12) \
+ RUN3M(int8_t, 13) \
+ RUN3(uint8_t, 14) \
RUN3M(int16_t, 13) \
RUN3(uint16_t, 14) \
RUN3M(int32_t, 15) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
index fc76d1c3b3e..70ea8ef65cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vor-template.h"
-/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
index ae115a2f503..44d09a2bddc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vor-template.h"
-/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
index e60146cc232..3daad2e8890 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
@@ -32,20 +32,25 @@
dst[i] = a[i] | -16; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
TEST2_TYPE(uint32_t) \
TEST2_TYPE(int64_t) \
TEST2_TYPE(uint64_t) \
+ TEST3M_TYPE(int8_t) \
+ TEST3_TYPE(uint8_t) \
TEST3M_TYPE(int16_t) \
TEST3_TYPE(uint16_t) \
TEST3M_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
index 4a4c064e101..58b69ec393e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
@@ -28,12 +28,16 @@
assert (as##TYPE[i] == 89 % VAL);
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
index df99f5019fb..7d2b478e1de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
@@ -4,7 +4,7 @@
#include "vrem-template.h"
/* Currently we use an epilogue loop which also contains vrems. Therefore we
- expect 10 vrem[u]s instead of 6. */
+ expect 14 vrem[u]s instead of 8. */
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
index 3cff13a47e4..b7bc1ccb860 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
@@ -4,7 +4,7 @@
#include "vrem-template.h"
/* Currently we use an epilogue loop which also contains vrems. Therefore we
- expect 10 vrem[u]s instead of 6. */
+ expect 14 vrem[u]s instead of 8. */
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
index d5ef40667ff..9c4e6acae99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
@@ -16,14 +16,17 @@
dst[i] = a[i] % b; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
index 4f254872e33..fb6df757c90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
@@ -12,20 +12,20 @@
TYPE b##TYPE[SZ]; \
for (int i = 0; i < SZ; i++) \
{ \
- a##TYPE[i] = 999; \
+ a##TYPE[i] = 123; \
b##TYPE[i] = VAL; \
} \
vsub_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
for (int i = 0; i < SZ; i++) \
- assert (a##TYPE[i] == 999 - VAL);
+ assert (a##TYPE[i] == 123 - VAL);
#define RUN2(TYPE,VAL) \
TYPE as##TYPE[SZ]; \
for (int i = 0; i < SZ; i++) \
- as##TYPE[i] = 999; \
+ as##TYPE[i] = 123; \
vsubs_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \
for (int i = 0; i < SZ; i++) \
- assert (as##TYPE[i] == 999 - VAL);
+ assert (as##TYPE[i] == 123 - VAL);
#define RUN3(TYPE) \
TYPE as2##TYPE[SZ]; \
@@ -44,24 +44,32 @@
assert (as3##TYPE[i] == (TYPE)(15 - (i * -17 + 667)));
#define RUN_ALL() \
+ RUN(int8_t, 1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, 1) \
RUN(uint16_t, 2) \
RUN(int32_t, 3) \
RUN(uint32_t, 4) \
RUN(int64_t, 5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, 7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, 7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, 9) \
RUN2(uint32_t, 10) \
RUN2(int64_t, 11) \
RUN2(uint64_t, 12) \
+ RUN3(int8_t) \
+ RUN3(uint8_t) \
RUN3(int16_t) \
RUN3(uint16_t) \
RUN3(int32_t) \
RUN3(uint32_t) \
RUN3(int64_t) \
RUN3(uint64_t) \
+ RUN4(int8_t) \
+ RUN4(uint8_t) \
RUN4(int16_t) \
RUN4(uint16_t) \
RUN4(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
index a0d3802be65..5641432410e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vsub-template.h"
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
index 562c026a7e4..4fe0969c3a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vsub-template.h"
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
index 47f07f13462..222972d4752 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
@@ -32,26 +32,36 @@
dst[i] = 15 - a[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
TEST2_TYPE(uint32_t) \
TEST2_TYPE(int64_t) \
TEST2_TYPE(uint64_t)
+
+ TEST3_TYPE(int8_t) \
+ TEST3_TYPE(uint8_t) \
TEST3_TYPE(int16_t) \
TEST3_TYPE(uint16_t) \
TEST3_TYPE(int32_t) \
TEST3_TYPE(uint32_t) \
TEST3_TYPE(int64_t) \
TEST3_TYPE(uint64_t) \
+
+ TEST4_TYPE(int8_t) \
+ TEST4_TYPE(uint8_t) \
TEST4_TYPE(int16_t) \
TEST4_TYPE(uint16_t) \
TEST4_TYPE(int32_t) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
index ab0975a6408..7239733d12c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
@@ -44,18 +44,24 @@
assert (aim##TYPE[i] == (VAL ^ -16));
#define RUN_ALL() \
+ RUN(int8_t, -1) \
+ RUN(uint8_t, 2) \
RUN(int16_t, -1) \
RUN(uint16_t, 2) \
RUN(int32_t, -3) \
RUN(uint32_t, 4) \
RUN(int64_t, -5) \
RUN(uint64_t, 6) \
+ RUN2(int8_t, -7) \
+ RUN2(uint8_t, 8) \
RUN2(int16_t, -7) \
RUN2(uint16_t, 8) \
RUN2(int32_t, -9) \
RUN2(uint32_t, 10) \
RUN2(int64_t, -11) \
RUN2(uint64_t, 12) \
+ RUN3M(int8_t, 13) \
+ RUN3(uint8_t, 14) \
RUN3M(int16_t, 13) \
RUN3(uint16_t, 14) \
RUN3M(int32_t, 15) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
index fbef4a45770..83b223e987f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
@@ -3,5 +3,5 @@
#include "vxor-template.h"
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
index 9729ad14eb1..6ba007c9d90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
@@ -3,5 +3,5 @@
#include "vxor-template.h"
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
index 370b242f197..b36698b5311 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
@@ -32,20 +32,25 @@
dst[i] = a[i] ^ -16; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
TEST_TYPE(uint32_t) \
TEST_TYPE(int64_t) \
TEST_TYPE(uint64_t) \
+ TEST2_TYPE(int8_t) \
+ TEST2_TYPE(uint8_t) \
TEST2_TYPE(int16_t) \
TEST2_TYPE(uint16_t) \
TEST2_TYPE(int32_t) \
TEST2_TYPE(uint32_t) \
TEST2_TYPE(int64_t) \
TEST2_TYPE(uint64_t) \
+ TEST3M_TYPE(int8_t) \
+ TEST3_TYPE(uint8_t) \
TEST3M_TYPE(int16_t) \
TEST3_TYPE(uint16_t) \
TEST3M_TYPE(int32_t) \
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2023-06-19 11:42 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add (u)int8_t to binop tests Jeff Law
2023-07-14 2:46 Jeff Law
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