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* [gcc r14-1956] RISC-V: Add tuple vector mode psABI checking and simplify code
@ 2023-06-20 1:15 Pan Li
0 siblings, 0 replies; only message in thread
From: Pan Li @ 2023-06-20 1:15 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1d2308d68571ad7f84b2319574f381c486a58a3a
commit r14-1956-g1d2308d68571ad7f84b2319574f381c486a58a3a
Author: Lehua Ding <lehua.ding@rivai.ai>
Date: Sun Jun 18 19:41:57 2023 +0800
RISC-V: Add tuple vector mode psABI checking and simplify code
Hi,
This patch does several things:
1. Adds the missed checking of tuple vector mode
2. Extend the scope of checking to all vector types, previously it
was only for scalable vector types.
3. Simplify the logic of determining code of vector type which will lower to
vector tmode code
Best,
Lehua
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_scalable_vector_type_p): Delete.
(riscv_arg_has_vector): Simplify.
(riscv_pass_in_vector_p): Adjust warning message.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Add -Wno-psabi option.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Ditto.
* gcc.target/riscv/rvv/base/pr110119-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr110119-2.c: Ditto.
* gcc.target/riscv/vector-abi-1.c: Ditto.
* gcc.target/riscv/vector-abi-2.c: Ditto.
* gcc.target/riscv/vector-abi-3.c: Ditto.
* gcc.target/riscv/vector-abi-4.c: Ditto.
* gcc.target/riscv/vector-abi-5.c: Ditto.
* gcc.target/riscv/vector-abi-6.c: Ditto.
* gcc.target/riscv/vector-abi-7.c: New test.
* gcc.target/riscv/vector-abi-8.c: New test.
* gcc.target/riscv/vector-abi-9.c: New test.
Diff:
---
gcc/config/riscv/riscv.cc | 53 +++++++---------------
.../gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-7.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-7.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm-7.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-7.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110119-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110119-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 9 +++-
gcc/testsuite/gcc.target/riscv/vector-abi-6.c | 2 +-
gcc/testsuite/gcc.target/riscv/vector-abi-7.c | 14 ++++++
gcc/testsuite/gcc.target/riscv/vector-abi-8.c | 14 ++++++
gcc/testsuite/gcc.target/riscv/vector-abi-9.c | 16 +++++++
41 files changed, 104 insertions(+), 74 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8d5b4c163d3..6eb63a9d4de 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3806,31 +3806,22 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2))));
}
-/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
- intrinsic vector type. Because we can't get the decl for the params. */
-
-static bool
-riscv_scalable_vector_type_p (const_tree type)
-{
- tree size = TYPE_SIZE (type);
- if (size && TREE_CODE (size) == INTEGER_CST)
- return false;
-
- /* For the data type like vint32m1_t, the size code is POLY_INT_CST. */
- return true;
-}
+/* Return true if a vector type is included in the type TYPE. */
static bool
riscv_arg_has_vector (const_tree type)
{
- bool is_vector = false;
+ if (riscv_v_ext_mode_p (TYPE_MODE (type)))
+ return true;
+
+ if (!COMPLETE_TYPE_P (type))
+ return false;
switch (TREE_CODE (type))
{
case RECORD_TYPE:
- if (!COMPLETE_TYPE_P (type))
- break;
-
+ /* If it is a record, it is further determined whether its fileds have
+ vector type. */
for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
if (TREE_CODE (f) == FIELD_DECL)
{
@@ -3838,25 +3829,15 @@ riscv_arg_has_vector (const_tree type)
if (!TYPE_P (field_type))
break;
- /* Ignore it if it's fixed length vector. */
- if (VECTOR_TYPE_P (field_type))
- is_vector = riscv_scalable_vector_type_p (field_type);
- else
- is_vector = riscv_arg_has_vector (field_type);
+ if (riscv_arg_has_vector (field_type))
+ return true;
}
-
- break;
-
- case VECTOR_TYPE:
- is_vector = riscv_scalable_vector_type_p (type);
- break;
-
- default:
- is_vector = false;
break;
+ case ARRAY_TYPE:
+ return riscv_arg_has_vector (TREE_TYPE (type));
}
- return is_vector;
+ return false;
}
/* Pass the type to check whether it's a vector type or contains vector type.
@@ -3867,11 +3848,11 @@ riscv_pass_in_vector_p (const_tree type)
{
static int warned = 0;
- if (type && riscv_arg_has_vector (type) && !warned)
+ if (type && riscv_v_ext_mode_p (TYPE_MODE (type)) && !warned)
{
- warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
- "experimental stage and may changes in the upcoming version of "
- "GCC.");
+ warning (OPT_Wpsabi,
+ "ABI for the vector type is currently in experimental stage and "
+ "may changes in the upcoming version of GCC.");
warned = 1;
}
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
index 09e8396936e..61eac38e541 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
index efeb23e9719..3e3ecd1ef56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
index 35b2aa8aee9..f07b65801a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
index 957d5b26fdc..57bf8fae686 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
index 398d0dcc649..8bc29c3df85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
index 4d1b9e29b7d..f6140fbc395 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
index 43acea6c345..7ab4bca7dea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
index 2f38c3d13f5..a50102678d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
index 7449f63583c..d6e8248ba0b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
index 248a30433a5..08506e336d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
index a587dd45eb1..ff92c3926e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
index 18dedb0f77d..86a3f2df7b3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
index 61dbd5b4f2b..a64f82fbab7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
index da7c462e0c3..6193d2a6c52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
index 7aaa6b37d52..267c1ac7728 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "merge-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
index 58c2cd8ce23..b361a04836e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
index d88b6461da5..9e9123a6cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
index 110df490c6e..0cefb241647 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
index aa328810c30..9df69a0cc2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
index 7117a492dc7..e03f8e1ad51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
index 67b2e6f680e..c74ad03935e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
index 0ac98287254..46c4a71256d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
#include "perm.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
index cb216a9543c..8fe80e6d54c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
index 1b51b315ad1..04906d3c4fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
index 4cae7f4f1a5..f5e9f9e5919 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
index e60b19fab68..8460491b810 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
index b61990915b0..5394dec2045 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
index b23df90f0ac..cee7efc3aa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
#include "perm-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
index d935d36bf69..49b25830b8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0 -Wno-psabi" } */
#include "perm-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
index f16502bcfee..c5d9b1538cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
index b233ff1e904..958d1addb05 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gczve32x --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
#include <stdint.h>
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
index 969f14277a4..114ee6de483 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -4,7 +4,7 @@
#include "riscv_vector.h"
void
-fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
void
bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
index 63d97d30fc5..0b24ccb8312 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -5,7 +5,7 @@
#include "riscv_vector.h"
vint32m1_t
-fun (vint32m1_t* a) { return *a; } /* { dg-warning "the scalable vector type" } */
+fun (vint32m1_t* a) { return *a; } /* { dg-warning "the vector type" } */
void
bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
index 90ece60cc6f..844a5db4027 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -4,7 +4,7 @@
#include "riscv_vector.h"
vint32m1_t*
-fun (vint32m1_t* a) { return a; } /* { dg-bogus "the scalable vector type" } */
+fun (vint32m1_t* a) { return a; } /* { dg-bogus "the vector type" } */
void
bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
index ecf6d4cc26b..a5dc2dffaac 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -6,7 +6,7 @@
typedef int v4si __attribute__ ((vector_size (16)));
v4si
-fun (v4si a) { return a; } /* { dg-bogus "the scalable vector type" } */
+fun (v4si a) { return a; } /* { dg-bogus "the vector type" } */
void
bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
index 6053e0783b6..9dc69518b5d 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -2,10 +2,15 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
typedef int v4si __attribute__ ((vector_size (16)));
-struct A { int a; v4si b; };
+struct A { int a; int b; };
+
+void foo (int b);
void
-fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+fun (struct A a) {
+
+ foo (a.b);
+} /* { dg-bogus "the vector type" } */
void
bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
index 63bc4a89805..3a65f2c60ab 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
@@ -12,7 +12,7 @@ foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
vl = __riscv_vsetvlmax_e16mf2();
for (size_t i = 0; i < n; i += 1)
{
- vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
+ vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the vector type" } */
vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
__riscv_vse32_v_i32m1(out, c, vl);
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-7.c b/gcc/testsuite/gcc.target/riscv/vector-abi-7.c
new file mode 100644
index 00000000000..2795fd4f9fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-7.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1x3_t a) { } /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+ vint32m1x3_t a;
+ fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-8.c b/gcc/testsuite/gcc.target/riscv/vector-abi-8.c
new file mode 100644
index 00000000000..9cf68d4da9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-8.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1x3_t*
+fun (vint32m1x3_t* a) { return a; } /* { dg-bogus "the vector type" } */
+
+void
+bar ()
+{
+ vint32m1x3_t a;
+ fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-9.c b/gcc/testsuite/gcc.target/riscv/vector-abi-9.c
new file mode 100644
index 00000000000..b5f130f0caf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-9.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) { return a; } /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+ v4si a;
+ fun (a);
+}
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