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* [gcc r12-9719] aarch64: Fix wrong code with st64b builtin [PR110100]
@ 2023-06-22 10:19 Alex Coplan
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From: Alex Coplan @ 2023-06-22 10:19 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0112ed013847ca9dbef4ba21f1c3f94c5bbe310b
commit r12-9719-g0112ed013847ca9dbef4ba21f1c3f94c5bbe310b
Author: Alex Coplan <alex.coplan@arm.com>
Date: Tue Jun 6 11:52:19 2023 +0100
aarch64: Fix wrong code with st64b builtin [PR110100]
The st64b pattern incorrectly had an output constraint on the register
operand containing the destination address for the store, leading to
wrong code. This patch fixes that.
gcc/ChangeLog:
PR target/110100
* config/aarch64/aarch64-builtins.cc (aarch64_expand_builtin_ls64):
Use input operand for the destination address.
* config/aarch64/aarch64.md (st64b): Fix constraint on address
operand.
gcc/testsuite/ChangeLog:
PR target/110100
* gcc.target/aarch64/acle/pr110100.c: New test.
(cherry picked from commit 737a0b749a7bc3e7cb904ea2d4b18dc130514b85)
Diff:
---
gcc/config/aarch64/aarch64-builtins.cc | 2 +-
gcc/config/aarch64/aarch64.md | 2 +-
gcc/testsuite/gcc.target/aarch64/acle/pr110100.c | 7 +++++++
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
index 06738d22691..d8b69e802ed 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -2291,7 +2291,7 @@ aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target)
{
rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
- create_output_operand (&ops[0], op0, DImode);
+ create_input_operand (&ops[0], op0, DImode);
create_input_operand (&ops[1], op1, V8DImode);
expand_insn (CODE_FOR_st64b, 2, ops);
return const0_rtx;
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d89b2badba7..b9b3ba4f916 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -7678,7 +7678,7 @@
)
(define_insn "st64b"
- [(set (mem:V8DI (match_operand:DI 0 "register_operand" "=r"))
+ [(set (mem:V8DI (match_operand:DI 0 "register_operand" "r"))
(unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")]
UNSPEC_ST64B)
)]
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c b/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c
new file mode 100644
index 00000000000..f56d5e619e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.7-a -O2" } */
+#include <arm_acle.h>
+void do_st64b(data512_t data) {
+ __arm_st64b((void*)0x10000000, data);
+}
+/* { dg-final { scan-assembler {mov\tx([123])?[0-9], 268435456} } } */
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