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* [gcc(refs/users/meissner/heads/work123)] Update ChangeLog.meissner
@ 2023-06-23 15:47 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2023-06-23 15:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:fa318fbba811e64ad6922dc5226bf87a75ebd036
commit fa318fbba811e64ad6922dc5226bf87a75ebd036
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jun 23 08:39:55 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 97dbc8ac35e..3ad68217d6d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,5 @@
+==================== Branch work123, merge up 06/23/2023 ====================
+
==================== Branch work123, patch #1 ====================
Fix power10 fusion bug with prefixed loads, PR target/105325
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work123)] Update ChangeLog.meissner
@ 2023-06-23 15:48 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2023-06-23 15:48 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2799ef1636b4188e1d911c8ca105da3756d7542f
commit 2799ef1636b4188e1d911c8ca105da3756d7542f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jun 23 11:48:44 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 3ad68217d6d..2be5b59023c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,4 @@
-==================== Branch work123, merge up 06/23/2023 ====================
+==================== Branch work123, merge up 06/23/2023 (patch #1 included) ====================
==================== Branch work123, patch #1 ====================
@@ -66,10 +66,12 @@ The solution involves:
longer using ds_form_mem_operand, the ld and lwa instructions will fuse
x-form (reg+reg) addresses in addition ds-form (reg+offset or reg).
-2023-06-22 Michael Meissner <meissner@linux.ibm.com>
+2023-06-23 Michael Meissner <meissner@linux.ibm.com>
+
gcc/
+ PR target/105325
* config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that
allowed prefixed lwa to be generated.
* config/rs6000/fusion.md: Regenerate.
@@ -80,9 +82,11 @@ gcc/
gcc/testsuite/
+ PR target/105325
* g++.target/powerpc/pr105325.C: New test.
- * gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c: Update insn
- counts.
+ * cc.target/powerpc/fusion-p10-ldcmpi.c: Update insn counts.
+
+Co-Authored-By: Aaron Sawdey <acsawdey@linux.ibm.com>
==================== Branch work123, baseline ====================
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work123)] Update ChangeLog.meissner
@ 2023-06-23 15:47 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2023-06-23 15:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a926b6ccc11fee0437ee27fda23c529f54b9fb37
commit a926b6ccc11fee0437ee27fda23c529f54b9fb37
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jun 23 08:35:26 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 1935c34ea01..97dbc8ac35e 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,87 @@
+==================== Branch work123, patch #1 ====================
+
+Fix power10 fusion bug with prefixed loads, PR target/105325
+
+This changes fixes PR target/105325. PR target/105325 is a bug where an
+invalid lwa instruction is generated due to power10 fusion of a load
+instruction to a GPR and an compare immediate instruction with the immediate
+being -1, 0, or 1.
+
+In some cases, when the load instruction is done, the GCC compiler would
+generate a load instruction with an offset that was too large to fit into the
+normal load instruction.
+
+In particular, loads from the stack might originally have a small offset, so
+that the load is not a prefixed load. However, after the stack is set up, and
+register allocation has been done, the offset now is large enough that we would
+have to use a prefixed load instruction.
+
+The support for prefixed loads did not consider that patterns with a fused load
+and compare might have a prefixed address. Without this support, the proper
+prefixed load won't be generated.
+
+In the original code, when the split2 pass is run after reload has finished the
+ds_form_mem_operand predicate that was used for lwa and ld no longer returns
+true. When the pattern was created, ds_form_mem_operand recognized the insn as
+being valid since the offset was small. But after register allocation,
+ds_form_mem_operand did not return true. Because it didn't return true, the
+insn could not be split. Since the insn was not split and the prefix support
+did not indicate a prefixed instruction was used, the wrong load is generated.
+
+The solution involves:
+
+ 1) Don't use ds_form_mem_operand for ld and lwa, always use
+ non_update_memory_operand.
+
+ 2) Delete ds_form_mem_operand since it is no longer used.
+
+ 3) Use the "YZ" constraints for ld/lwa instead of "m".
+
+ 4) If we don't need to sign extend the lwa, convert it to lwz, and use
+ cmpwi instead of cmpdi. Adjust the insn name to reflect the code
+ generate.
+
+ 5) Insure that the insn using lwa will be recognized as having a prefixed
+ operand (and hence the insn length will be 16 bytes instead of 8
+ bytes).
+
+ 5a) Set the prefixed and maybe_prefix attributes to know that
+ fused_load_cmpi are also load insns;
+
+ 5b) In the case where we are just setting CC and not using the memory
+ afterward, set the clobber to use a DI register, and put an
+ explicit sign_extend operation in the split;
+
+ 5c) Set the sign_extend attribute to "yes" for lwa.
+
+ 5d) 5a-5c are the things that prefixed_load_p in rs6000.cc checks to
+ ensure that lwa is treated as a ds-form instruction and not as
+ a d-form instruction (i.e. lwz).
+
+ 6) Add a new test case for this case.
+
+ 7) Adjust the insn counts in fusion-p10-ldcmpi.c. Because we are no
+ longer using ds_form_mem_operand, the ld and lwa instructions will fuse
+ x-form (reg+reg) addresses in addition ds-form (reg+offset or reg).
+
+2023-06-22 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that
+ allowed prefixed lwa to be generated.
+ * config/rs6000/fusion.md: Regenerate.
+ * config/rs6000/predicates.md (ds_form_mem_operand): Delete.
+ * config/rs6000/rs6000.md (prefixed attribute): Add support for load
+ plus compare immediate fused insns.
+ (maybe_prefixed): Likewise.
+
+gcc/testsuite/
+
+ * g++.target/powerpc/pr105325.C: New test.
+ * gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c: Update insn
+ counts.
+
==================== Branch work123, baseline ====================
2023-06-22 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work123)] Update ChangeLog.meissner
@ 2023-06-23 12:39 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2023-06-23 12:39 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:67f08f3831bf0621009366dfdf71d30d14ede923
commit 67f08f3831bf0621009366dfdf71d30d14ede923
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jun 23 08:39:55 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 97dbc8ac35e..3ad68217d6d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,5 @@
+==================== Branch work123, merge up 06/23/2023 ====================
+
==================== Branch work123, patch #1 ====================
Fix power10 fusion bug with prefixed loads, PR target/105325
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work123)] Update ChangeLog.meissner
@ 2023-06-23 12:38 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2023-06-23 12:38 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:371dff4b847b5fd0ebba767aa573fb80c3deaf59
commit 371dff4b847b5fd0ebba767aa573fb80c3deaf59
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jun 23 08:35:26 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 1935c34ea01..97dbc8ac35e 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,87 @@
+==================== Branch work123, patch #1 ====================
+
+Fix power10 fusion bug with prefixed loads, PR target/105325
+
+This changes fixes PR target/105325. PR target/105325 is a bug where an
+invalid lwa instruction is generated due to power10 fusion of a load
+instruction to a GPR and an compare immediate instruction with the immediate
+being -1, 0, or 1.
+
+In some cases, when the load instruction is done, the GCC compiler would
+generate a load instruction with an offset that was too large to fit into the
+normal load instruction.
+
+In particular, loads from the stack might originally have a small offset, so
+that the load is not a prefixed load. However, after the stack is set up, and
+register allocation has been done, the offset now is large enough that we would
+have to use a prefixed load instruction.
+
+The support for prefixed loads did not consider that patterns with a fused load
+and compare might have a prefixed address. Without this support, the proper
+prefixed load won't be generated.
+
+In the original code, when the split2 pass is run after reload has finished the
+ds_form_mem_operand predicate that was used for lwa and ld no longer returns
+true. When the pattern was created, ds_form_mem_operand recognized the insn as
+being valid since the offset was small. But after register allocation,
+ds_form_mem_operand did not return true. Because it didn't return true, the
+insn could not be split. Since the insn was not split and the prefix support
+did not indicate a prefixed instruction was used, the wrong load is generated.
+
+The solution involves:
+
+ 1) Don't use ds_form_mem_operand for ld and lwa, always use
+ non_update_memory_operand.
+
+ 2) Delete ds_form_mem_operand since it is no longer used.
+
+ 3) Use the "YZ" constraints for ld/lwa instead of "m".
+
+ 4) If we don't need to sign extend the lwa, convert it to lwz, and use
+ cmpwi instead of cmpdi. Adjust the insn name to reflect the code
+ generate.
+
+ 5) Insure that the insn using lwa will be recognized as having a prefixed
+ operand (and hence the insn length will be 16 bytes instead of 8
+ bytes).
+
+ 5a) Set the prefixed and maybe_prefix attributes to know that
+ fused_load_cmpi are also load insns;
+
+ 5b) In the case where we are just setting CC and not using the memory
+ afterward, set the clobber to use a DI register, and put an
+ explicit sign_extend operation in the split;
+
+ 5c) Set the sign_extend attribute to "yes" for lwa.
+
+ 5d) 5a-5c are the things that prefixed_load_p in rs6000.cc checks to
+ ensure that lwa is treated as a ds-form instruction and not as
+ a d-form instruction (i.e. lwz).
+
+ 6) Add a new test case for this case.
+
+ 7) Adjust the insn counts in fusion-p10-ldcmpi.c. Because we are no
+ longer using ds_form_mem_operand, the ld and lwa instructions will fuse
+ x-form (reg+reg) addresses in addition ds-form (reg+offset or reg).
+
+2023-06-22 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that
+ allowed prefixed lwa to be generated.
+ * config/rs6000/fusion.md: Regenerate.
+ * config/rs6000/predicates.md (ds_form_mem_operand): Delete.
+ * config/rs6000/rs6000.md (prefixed attribute): Add support for load
+ plus compare immediate fused insns.
+ (maybe_prefixed): Likewise.
+
+gcc/testsuite/
+
+ * g++.target/powerpc/pr105325.C: New test.
+ * gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c: Update insn
+ counts.
+
==================== Branch work123, baseline ====================
2023-06-22 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work123)] Update ChangeLog.meissner
@ 2023-06-23 12:35 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2023-06-23 12:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e645240b1789bbeb12d7e7c7112f9c4cbd89ba46
commit e645240b1789bbeb12d7e7c7112f9c4cbd89ba46
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jun 23 08:35:26 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 1935c34ea01..97dbc8ac35e 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,87 @@
+==================== Branch work123, patch #1 ====================
+
+Fix power10 fusion bug with prefixed loads, PR target/105325
+
+This changes fixes PR target/105325. PR target/105325 is a bug where an
+invalid lwa instruction is generated due to power10 fusion of a load
+instruction to a GPR and an compare immediate instruction with the immediate
+being -1, 0, or 1.
+
+In some cases, when the load instruction is done, the GCC compiler would
+generate a load instruction with an offset that was too large to fit into the
+normal load instruction.
+
+In particular, loads from the stack might originally have a small offset, so
+that the load is not a prefixed load. However, after the stack is set up, and
+register allocation has been done, the offset now is large enough that we would
+have to use a prefixed load instruction.
+
+The support for prefixed loads did not consider that patterns with a fused load
+and compare might have a prefixed address. Without this support, the proper
+prefixed load won't be generated.
+
+In the original code, when the split2 pass is run after reload has finished the
+ds_form_mem_operand predicate that was used for lwa and ld no longer returns
+true. When the pattern was created, ds_form_mem_operand recognized the insn as
+being valid since the offset was small. But after register allocation,
+ds_form_mem_operand did not return true. Because it didn't return true, the
+insn could not be split. Since the insn was not split and the prefix support
+did not indicate a prefixed instruction was used, the wrong load is generated.
+
+The solution involves:
+
+ 1) Don't use ds_form_mem_operand for ld and lwa, always use
+ non_update_memory_operand.
+
+ 2) Delete ds_form_mem_operand since it is no longer used.
+
+ 3) Use the "YZ" constraints for ld/lwa instead of "m".
+
+ 4) If we don't need to sign extend the lwa, convert it to lwz, and use
+ cmpwi instead of cmpdi. Adjust the insn name to reflect the code
+ generate.
+
+ 5) Insure that the insn using lwa will be recognized as having a prefixed
+ operand (and hence the insn length will be 16 bytes instead of 8
+ bytes).
+
+ 5a) Set the prefixed and maybe_prefix attributes to know that
+ fused_load_cmpi are also load insns;
+
+ 5b) In the case where we are just setting CC and not using the memory
+ afterward, set the clobber to use a DI register, and put an
+ explicit sign_extend operation in the split;
+
+ 5c) Set the sign_extend attribute to "yes" for lwa.
+
+ 5d) 5a-5c are the things that prefixed_load_p in rs6000.cc checks to
+ ensure that lwa is treated as a ds-form instruction and not as
+ a d-form instruction (i.e. lwz).
+
+ 6) Add a new test case for this case.
+
+ 7) Adjust the insn counts in fusion-p10-ldcmpi.c. Because we are no
+ longer using ds_form_mem_operand, the ld and lwa instructions will fuse
+ x-form (reg+reg) addresses in addition ds-form (reg+offset or reg).
+
+2023-06-22 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that
+ allowed prefixed lwa to be generated.
+ * config/rs6000/fusion.md: Regenerate.
+ * config/rs6000/predicates.md (ds_form_mem_operand): Delete.
+ * config/rs6000/rs6000.md (prefixed attribute): Add support for load
+ plus compare immediate fused insns.
+ (maybe_prefixed): Likewise.
+
+gcc/testsuite/
+
+ * g++.target/powerpc/pr105325.C: New test.
+ * gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c: Update insn
+ counts.
+
==================== Branch work123, baseline ====================
2023-06-22 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
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