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* [gcc r14-2078] RISC-V: fix expand function of vlmul_ext RVV intrinsic
@ 2023-06-25 13:53 Pan Li
0 siblings, 0 replies; only message in thread
From: Pan Li @ 2023-06-25 13:53 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b23ec2de3b992784c3e376da8f51f962daca4d86
commit r14-2078-gb23ec2de3b992784c3e376da8f51f962daca4d86
Author: Li Xu <xuli1@eswincomputing.com>
Date: Sun Jun 25 09:09:32 2023 +0000
RISC-V: fix expand function of vlmul_ext RVV intrinsic
Consider this following case:
void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
}
Compilation fails with:
test.c: In function 'test_vlmul_ext_v_i8mf8_i8mf4':
test.c:5:1: error: unrecognizable insn:
5 | }
| ^
(insn 30 29 0 2 (set (mem/c:VNx2QI (reg/f:DI 143) [0 x+0 S[2, 2] A32])
(mem/c:VNx2QI (reg/f:DI 148) [0 op1+0 S[2, 2] A16])) "test.c":4:18 -1
(nil))
during RTL pass: vregs
test.c:5:1: internal compiler error: in extract_insn, at recog.cc:2791
0x7c61b8 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
../.././riscv-gcc/gcc/rtl-error.cc:108
0x7c61d7 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
../.././riscv-gcc/gcc/rtl-error.cc:116
0xed58a7 extract_insn(rtx_insn*)
../.././riscv-gcc/gcc/recog.cc:2791
0xb7f789 instantiate_virtual_regs_in_insn
../.././riscv-gcc/gcc/function.cc:1611
0xb7f789 instantiate_virtual_regs
../.././riscv-gcc/gcc/function.cc:1984
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: change emit_insn to
emit_move_insn
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-2.c: New test.
Diff:
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c | 8 ++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index c6c53dc13a5..5c8deda900d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1567,7 +1567,7 @@ public:
{
tree arg = CALL_EXPR_ARG (e.exp, 0);
rtx src = expand_normal (arg);
- emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src));
+ emit_move_insn (gen_lowpart (e.vector_mode (), e.target), src);
return e.target;
}
};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
new file mode 100644
index 00000000000..2b088b53546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+
+#include "riscv_vector.h"
+
+void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
+ vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
+}
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