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* [gcc r14-2136] RISC-V: Split VF iterators for Zvfh(min).
@ 2023-06-27 21:30 Robin Dapp
0 siblings, 0 replies; only message in thread
From: Robin Dapp @ 2023-06-27 21:30 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:201c6c322f3e88367ac9b6f476cf76b755d3c4b1
commit r14-2136-g201c6c322f3e88367ac9b6f476cf76b755d3c4b1
Author: Robin Dapp <rdapp@ventanamicro.com>
Date: Thu Jun 22 08:58:06 2023 +0200
RISC-V: Split VF iterators for Zvfh(min).
When working on FP widening/narrowing I realized the Zvfhmin handling
is not ideal right now: We use the "enabled" insn attribute to disable
instructions not available with Zvfhmin but only with Zvfh.
However, "enabled == 0" only disables insn alternatives, in our case all
of them when the mode is a HFmode. The insn itself remains available
(e.g. for combine to match) and we end up with an insn without alternatives
that reload cannot handle --> ICE.
The proper solution is to disable the instruction for the respective
mode altogether. This patch achieves this by splitting the VF as well
as VWEXTF iterators into variants with TARGET_ZVFH and
TARGET_VECTOR_ELEN_FP_16 (which is true when either TARGET_ZVFH or
TARGET_ZVFHMIN are true). Also, VWCONVERTI, VHF and VHF_LMUL1 need
adjustments.
gcc/ChangeLog:
* config/riscv/autovec.md: VF_AUTO -> VF.
* config/riscv/vector-iterators.md: Introduce VF_ZVFHMIN,
VWEXTF_ZVFHMIN and use TARGET_ZVFH in VWCONVERTI, VHF and
VHF_LMUL1.
* config/riscv/vector.md: Use new iterators.
Diff:
---
gcc/config/riscv/autovec.md | 156 +++++++++++++++++------------------
gcc/config/riscv/vector-iterators.md | 63 ++++++++------
gcc/config/riscv/vector.md | 20 ++---
3 files changed, 128 insertions(+), 111 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 19100b5b2cb..d7d049f3ecb 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -499,9 +499,9 @@
;; - vfneg.v/vfabs.v
;; -------------------------------------------------------------------------------
(define_expand "<optab><mode>2"
- [(set (match_operand:VF_AUTO 0 "register_operand")
- (any_float_unop_nofrm:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand")))]
+ [(set (match_operand:VF 0 "register_operand")
+ (any_float_unop_nofrm:VF
+ (match_operand:VF 1 "register_operand")))]
"TARGET_VECTOR"
{
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
@@ -516,9 +516,9 @@
;; - vfsqrt.v
;; -------------------------------------------------------------------------------
(define_expand "<optab><mode>2"
- [(set (match_operand:VF_AUTO 0 "register_operand")
- (any_float_unop:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand")))]
+ [(set (match_operand:VF 0 "register_operand")
+ (any_float_unop:VF
+ (match_operand:VF 1 "register_operand")))]
"TARGET_VECTOR"
{
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
@@ -648,39 +648,39 @@
(define_expand "fma<mode>4"
[(parallel
- [(set (match_operand:VF_AUTO 0 "register_operand")
- (fma:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand")
- (match_operand:VF_AUTO 2 "register_operand")
- (match_operand:VF_AUTO 3 "register_operand")))
+ [(set (match_operand:VF 0 "register_operand")
+ (fma:VF
+ (match_operand:VF 1 "register_operand")
+ (match_operand:VF 2 "register_operand")
+ (match_operand:VF 3 "register_operand")))
(clobber (match_dup 4))])]
"TARGET_VECTOR"
{
operands[4] = gen_reg_rtx (Pmode);
})
-(define_insn_and_split "*fma<VF_AUTO:mode><P:mode>"
- [(set (match_operand:VF_AUTO 0 "register_operand" "=vr, vr, ?&vr")
- (fma:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand" " %0, vr, vr")
- (match_operand:VF_AUTO 2 "register_operand" " vr, vr, vr")
- (match_operand:VF_AUTO 3 "register_operand" " vr, 0, vr")))
+(define_insn_and_split "*fma<VF:mode><P:mode>"
+ [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr")
+ (fma:VF
+ (match_operand:VF 1 "register_operand" " %0, vr, vr")
+ (match_operand:VF 2 "register_operand" " vr, vr, vr")
+ (match_operand:VF 3 "register_operand" " vr, 0, vr")))
(clobber (match_operand:P 4 "register_operand" "=r,r,r"))]
"TARGET_VECTOR"
"#"
"&& reload_completed"
[(const_int 0)]
{
- riscv_vector::emit_vlmax_vsetvl (<VF_AUTO:MODE>mode, operands[4]);
+ riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]);
if (which_alternative == 2)
emit_insn (gen_rtx_SET (operands[0], operands[3]));
rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
- riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (PLUS, <VF_AUTO:MODE>mode),
+ riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (PLUS, <VF:MODE>mode),
riscv_vector::RVV_TERNOP, ops, operands[4]);
DONE;
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<VF_AUTO:MODE>")])
+ (set_attr "mode" "<VF:MODE>")])
;; -------------------------------------------------------------------------
;; ---- [FP] VFNMSAC and VFNMSUB
@@ -692,41 +692,41 @@
(define_expand "fnma<mode>4"
[(parallel
- [(set (match_operand:VF_AUTO 0 "register_operand")
- (fma:VF_AUTO
- (neg:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand"))
- (match_operand:VF_AUTO 2 "register_operand")
- (match_operand:VF_AUTO 3 "register_operand")))
+ [(set (match_operand:VF 0 "register_operand")
+ (fma:VF
+ (neg:VF
+ (match_operand:VF 1 "register_operand"))
+ (match_operand:VF 2 "register_operand")
+ (match_operand:VF 3 "register_operand")))
(clobber (match_dup 4))])]
"TARGET_VECTOR"
{
operands[4] = gen_reg_rtx (Pmode);
})
-(define_insn_and_split "*fnma<VF_AUTO:mode><P:mode>"
- [(set (match_operand:VF_AUTO 0 "register_operand" "=vr, vr, ?&vr")
- (fma:VF_AUTO
- (neg:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand" " %0, vr, vr"))
- (match_operand:VF_AUTO 2 "register_operand" " vr, vr, vr")
- (match_operand:VF_AUTO 3 "register_operand" " vr, 0, vr")))
+(define_insn_and_split "*fnma<VF:mode><P:mode>"
+ [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr")
+ (fma:VF
+ (neg:VF
+ (match_operand:VF 1 "register_operand" " %0, vr, vr"))
+ (match_operand:VF 2 "register_operand" " vr, vr, vr")
+ (match_operand:VF 3 "register_operand" " vr, 0, vr")))
(clobber (match_operand:P 4 "register_operand" "=r,r,r"))]
"TARGET_VECTOR"
"#"
"&& reload_completed"
[(const_int 0)]
{
- riscv_vector::emit_vlmax_vsetvl (<VF_AUTO:MODE>mode, operands[4]);
+ riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]);
if (which_alternative == 2)
emit_insn (gen_rtx_SET (operands[0], operands[3]));
rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
- riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (PLUS, <VF_AUTO:MODE>mode),
+ riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (PLUS, <VF:MODE>mode),
riscv_vector::RVV_TERNOP, ops, operands[4]);
DONE;
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<VF_AUTO:MODE>")])
+ (set_attr "mode" "<VF:MODE>")])
;; -------------------------------------------------------------------------
;; ---- [FP] VFMSAC and VFMSUB
@@ -738,41 +738,41 @@
(define_expand "fms<mode>4"
[(parallel
- [(set (match_operand:VF_AUTO 0 "register_operand")
- (fma:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand")
- (match_operand:VF_AUTO 2 "register_operand")
- (neg:VF_AUTO
- (match_operand:VF_AUTO 3 "register_operand"))))
+ [(set (match_operand:VF 0 "register_operand")
+ (fma:VF
+ (match_operand:VF 1 "register_operand")
+ (match_operand:VF 2 "register_operand")
+ (neg:VF
+ (match_operand:VF 3 "register_operand"))))
(clobber (match_dup 4))])]
"TARGET_VECTOR"
{
operands[4] = gen_reg_rtx (Pmode);
})
-(define_insn_and_split "*fms<VF_AUTO:mode><P:mode>"
- [(set (match_operand:VF_AUTO 0 "register_operand" "=vr, vr, ?&vr")
- (fma:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand" " %0, vr, vr")
- (match_operand:VF_AUTO 2 "register_operand" " vr, vr, vr")
- (neg:VF_AUTO
- (match_operand:VF_AUTO 3 "register_operand" " vr, 0, vr"))))
+(define_insn_and_split "*fms<VF:mode><P:mode>"
+ [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr")
+ (fma:VF
+ (match_operand:VF 1 "register_operand" " %0, vr, vr")
+ (match_operand:VF 2 "register_operand" " vr, vr, vr")
+ (neg:VF
+ (match_operand:VF 3 "register_operand" " vr, 0, vr"))))
(clobber (match_operand:P 4 "register_operand" "=r,r,r"))]
"TARGET_VECTOR"
"#"
"&& reload_completed"
[(const_int 0)]
{
- riscv_vector::emit_vlmax_vsetvl (<VF_AUTO:MODE>mode, operands[4]);
+ riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]);
if (which_alternative == 2)
emit_insn (gen_rtx_SET (operands[0], operands[3]));
rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
- riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (MINUS, <VF_AUTO:MODE>mode),
+ riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (MINUS, <VF:MODE>mode),
riscv_vector::RVV_TERNOP, ops, operands[4]);
DONE;
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<VF_AUTO:MODE>")])
+ (set_attr "mode" "<VF:MODE>")])
;; -------------------------------------------------------------------------
;; ---- [FP] VFMSAC and VFMSUB
@@ -784,43 +784,43 @@
(define_expand "fnms<mode>4"
[(parallel
- [(set (match_operand:VF_AUTO 0 "register_operand")
- (fma:VF_AUTO
- (neg:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand"))
- (match_operand:VF_AUTO 2 "register_operand")
- (neg:VF_AUTO
- (match_operand:VF_AUTO 3 "register_operand"))))
+ [(set (match_operand:VF 0 "register_operand")
+ (fma:VF
+ (neg:VF
+ (match_operand:VF 1 "register_operand"))
+ (match_operand:VF 2 "register_operand")
+ (neg:VF
+ (match_operand:VF 3 "register_operand"))))
(clobber (match_dup 4))])]
"TARGET_VECTOR"
{
operands[4] = gen_reg_rtx (Pmode);
})
-(define_insn_and_split "*fnms<VF_AUTO:mode><P:mode>"
- [(set (match_operand:VF_AUTO 0 "register_operand" "=vr, vr, ?&vr")
- (fma:VF_AUTO
- (neg:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand" " %0, vr, vr"))
- (match_operand:VF_AUTO 2 "register_operand" " vr, vr, vr")
- (neg:VF_AUTO
- (match_operand:VF_AUTO 3 "register_operand" " vr, 0, vr"))))
+(define_insn_and_split "*fnms<VF:mode><P:mode>"
+ [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr")
+ (fma:VF
+ (neg:VF
+ (match_operand:VF 1 "register_operand" " %0, vr, vr"))
+ (match_operand:VF 2 "register_operand" " vr, vr, vr")
+ (neg:VF
+ (match_operand:VF 3 "register_operand" " vr, 0, vr"))))
(clobber (match_operand:P 4 "register_operand" "=r,r,r"))]
"TARGET_VECTOR"
"#"
"&& reload_completed"
[(const_int 0)]
{
- riscv_vector::emit_vlmax_vsetvl (<VF_AUTO:MODE>mode, operands[4]);
+ riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]);
if (which_alternative == 2)
emit_insn (gen_rtx_SET (operands[0], operands[3]));
rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
- riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (MINUS, <VF_AUTO:MODE>mode),
+ riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (MINUS, <VF:MODE>mode),
riscv_vector::RVV_TERNOP, ops, operands[4]);
DONE;
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<VF_AUTO:MODE>")])
+ (set_attr "mode" "<VF:MODE>")])
;; =========================================================================
;; == SELECT_VL
@@ -923,10 +923,10 @@
;; - vfadd.vf/vfsub.vf/...
;; -------------------------------------------------------------------------
(define_expand "<optab><mode>3"
- [(match_operand:VF_AUTO 0 "register_operand")
- (any_float_binop:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand")
- (match_operand:VF_AUTO 2 "register_operand"))]
+ [(match_operand:VF 0 "register_operand")
+ (any_float_binop:VF
+ (match_operand:VF 1 "register_operand")
+ (match_operand:VF 2 "register_operand"))]
"TARGET_VECTOR"
{
riscv_vector::emit_vlmax_fp_insn (code_for_pred (<CODE>, <MODE>mode),
@@ -940,10 +940,10 @@
;; - vfmin.vf/vfmax.vf
;; -------------------------------------------------------------------------
(define_expand "<optab><mode>3"
- [(match_operand:VF_AUTO 0 "register_operand")
- (any_float_binop_nofrm:VF_AUTO
- (match_operand:VF_AUTO 1 "register_operand")
- (match_operand:VF_AUTO 2 "register_operand"))]
+ [(match_operand:VF 0 "register_operand")
+ (any_float_binop_nofrm:VF
+ (match_operand:VF 1 "register_operand")
+ (match_operand:VF 2 "register_operand"))]
"TARGET_VECTOR"
{
riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 26c1bb7a3d6..173d9b91fbe 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -271,7 +271,7 @@
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
])
-(define_mode_iterator VF [
+(define_mode_iterator VF_ZVFHMIN [
(VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
(VNx2HF "TARGET_VECTOR_ELEN_FP_16")
(VNx4HF "TARGET_VECTOR_ELEN_FP_16")
@@ -295,11 +295,12 @@
;; This iterator is the same as above but with TARGET_VECTOR_ELEN_FP_16
;; changed to TARGET_ZVFH. TARGET_VECTOR_ELEN_FP_16 is also true for
-;; TARGET_ZVFHMIN while we actually disable all instructions apart from
-;; load, store and convert for it.
-;; Consequently the autovec expanders should also only be enabled with
-;; TARGET_ZVFH.
-(define_mode_iterator VF_AUTO [
+;; TARGET_ZVFHMIN while we actually want to disable all instructions apart
+;; from load, store and convert for it.
+;; It is not enough to set the "enabled" attribute to false
+;; since this will only disable insn alternatives in reload but still
+;; allow the instruction and mode to be matched during combine et al.
+(define_mode_iterator VF [
(VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
(VNx2HF "TARGET_ZVFH")
(VNx4HF "TARGET_ZVFH")
@@ -494,7 +495,8 @@
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
])
-(define_mode_iterator VWEXTF [
+;; Same iterator split reason as VF_ZVFHMIN and VF.
+(define_mode_iterator VWEXTF_ZVFHMIN [
(VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_16")
(VNx4SF "TARGET_VECTOR_ELEN_FP_16")
@@ -509,13 +511,28 @@
(VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VWEXTF [
+ (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH")
+ (VNx4SF "TARGET_ZVFH")
+ (VNx8SF "TARGET_ZVFH")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -960,13 +977,13 @@
])
(define_mode_iterator VHF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
])
(define_mode_iterator VSF [
@@ -1010,9 +1027,9 @@
])
(define_mode_iterator VHF_LMUL1 [
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx8HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+ (VNx4HF "TARGET_ZVFH && TARGET_MIN_VLEN == 64")
+ (VNx2HF "TARGET_ZVFH && TARGET_MIN_VLEN == 32")
])
(define_mode_iterator VSF_LMUL1 [
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 674e602dec6..8f735c30c35 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1353,8 +1353,8 @@
(set_attr "mode" "<MODE>")])
(define_insn "*pred_broadcast<mode>"
- [(set (match_operand:VF 0 "register_operand" "=vr, vr, vr, vr, vr, vr, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:VF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, vr, vr")
+ (if_then_else:VF_ZVFHMIN
(unspec:<VM>
[(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
(match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
@@ -1363,9 +1363,9 @@
(match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (vec_duplicate:VF
+ (vec_duplicate:VF_ZVFHMIN
(match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
- (match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
+ (match_operand:VF_ZVFHMIN 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"@
vfmv.v.f\t%0,%3
@@ -7110,8 +7110,8 @@
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VWEXTF_ZVFHMIN
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 4 "vector_length_operand" " rK, rK")
@@ -7120,9 +7120,9 @@
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
+ (float_extend:VWEXTF_ZVFHMIN
(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
@@ -7210,7 +7210,7 @@
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
@@ -7230,7 +7230,7 @@
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:<V_DOUBLE_TRUNC>
[(float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
+ (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.rod.f.f.w\t%0,%3%p1"
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2023-06-27 21:30 [gcc r14-2136] RISC-V: Split VF iterators for Zvfh(min) Robin Dapp
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