[gcc/devel/vineetg/optim-double-const-m0] RISC-V: optim const DF +0.0 store to mem [PR/110748]

[gcc/devel/vineetg/optim-double-const-m0] RISC-V: optim const DF +0.0 store to mem [PR/110748]

[Vineet Gupta]

https://gcc.gnu.org/g:b9c828431b0d1e49e8b3e3bdd3b5c27df102da79

commit b9c828431b0d1e49e8b3e3bdd3b5c27df102da79
Author: Vineet Gupta <vineetg@rivosinc.com>
Date:   Thu Jul 20 13:55:35 2023 -0700

    RISC-V: optim const DF +0.0 store to mem [PR/110748]
    
    DF +0.0 is bitwise all zeros so int x0 store to mem can be used to optimize it.
    
    void zd(double *) { *d = 0.0; }
    
    currently:
    
    | fmv.d.x fa5,zero
    | fsd     fa5,0(a0)
    | ret
    
    With patch
    
    | sd      zero,0(a0)
    | ret
    
    Apparently this is a regression in gcc-13, introduced by commit
    ef85d150b5963 ("RISC-V: Enable TARGET_SUPPORTS_WIDE_INT") and the fix
    thus is a partial revert of that change.
    
    Ran thru full multilib testsuite and no regressions:
    
    gcc/Changelog:
    
            * config/riscv/predicates.md (const_0_operand): Add back
              const_double.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/pr110748-1.c: New Test.
    
    Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

Diff:
---
 gcc/config/riscv/predicates.md              |  2 +-
 gcc/testsuite/gcc.target/riscv/pr110748-1.c | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index eb975eaf994..28843b190fa 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -58,7 +58,7 @@
        (match_test "INTVAL (op) + 1 != 0")))
 
 (define_predicate "const_0_operand"
-  (and (match_code "const_int,const_wide_int,const_vector")
+  (and (match_code "const_int,const_wide_int,const_double,const_vector")
        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 
 (define_predicate "reg_or_0_operand"
diff --git a/gcc/testsuite/gcc.target/riscv/pr110748-1.c b/gcc/testsuite/gcc.target/riscv/pr110748-1.c
new file mode 100644
index 00000000000..0d482f07b33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr110748-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target hard_float } */
+/* { dg-options "-march=rv64g -mabi=lp64d -O2" } */
+
+
+void zd(double *d) { *d = 0.0;  }
+void zf(float *f) { *f = 0.0;  }
+
+/* { dg-final { scan-assembler-not "\tfmv\\.d\\.x\t" } } */
+/* { dg-final { scan-assembler-not "\tfmv\\.s\\.x\t" } } */