[gcc/devel/vineetg/optim-double-const-m0] RISC-V: Allow Expand to generate (set mem const_double -0.0)

[gcc/devel/vineetg/optim-double-const-m0] RISC-V: Allow Expand to generate (set mem const_double -0.0)

[Vineet Gupta]

https://gcc.gnu.org/g:d0cce78db02c396edda207027f391a98aeaf0375

commit d0cce78db02c396edda207027f391a98aeaf0375
Author: Vineet Gupta <vineetg@rivosinc.com>
Date:   Thu Jul 20 15:52:22 2023 -0700

    RISC-V: Allow Expand to generate (set mem const_double -0.0)
    
    | (insn 6 3 0 2 (set (mem:DF (reg/v/f:DI 134 [ d ]) [1 *d_2(D)+0 S8 A64])
    |        (const_double:DF -0.0 [-0x0.0p+0])) "neg.c":3:5 -1
    
    The first change is to adjust rtx cost of -0.0 to prevent generic expand code from
    forcing const to literal pool
    
       emit_move_insn
         compress_float_constant
            targetm.legitimate_constant_p
               riscv_legitimate_constant_p
                  riscv_const_insns
    
    second change ensures riscv_legitimize_move () doesn't force_reg ()
    const early.
    
    Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

Diff:
---
 gcc/config/riscv/riscv-protos.h |  1 +
 gcc/config/riscv/riscv.cc       | 23 +++++++++++++++++++++--
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 5766e3597e8..de61c468b3a 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -56,6 +56,7 @@ extern bool riscv_split_64bit_move_p (rtx, rtx);
 extern void riscv_split_doubleword_move (rtx, rtx);
 extern const char *riscv_output_move (rtx, rtx);
 extern const char *riscv_output_return ();
+extern bool riscv_const_double_p0_or_m0_rtx (rtx x);
 
 #ifdef RTX_CODE
 extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6e5d2feb103..9e22612604a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1274,7 +1274,8 @@ riscv_const_insns (rtx x)
 
     case CONST_DOUBLE:
       /* We can use x0 to load floating-point zero.  */
-      return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
+      return riscv_const_double_p0_or_m0_rtx(x) ? 1 : 0;
+
     case CONST_VECTOR:
       {
 	/* TODO: This is not accurate, we will need to
@@ -2142,6 +2143,22 @@ riscv_v_adjust_scalable_frame (rtx target, poly_int64 offset, bool epilogue)
   REG_NOTES (insn) = dwarf;
 }
 
+/* Return TRUE if rtx X is a FP constant 0.0 or -0.0.  */
+bool
+riscv_const_double_p0_or_m0_rtx (rtx x)
+{
+  const REAL_VALUE_TYPE *r;
+
+  if (GET_CODE (x) != CONST_DOUBLE)
+    return false;
+
+  r = CONST_DOUBLE_REAL_VALUE (x);
+  if (real_equal (r, &dconst0) || REAL_VALUE_MINUS_ZERO (*r))
+    return true;
+
+  return false;
+}
+
 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
    sequence that is valid.  */
 
@@ -2217,7 +2234,9 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
       return true;
     }
 
-  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
+  if (!register_operand (dest, mode)
+      && !reg_or_0_operand (src, mode)
+      && !riscv_const_double_p0_or_m0_rtx(src))
     {
       rtx reg;