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* [gcc r13-7667] RISC-V: Add AMO release bits
@ 2023-07-31 16:18 Patrick O'Neill
0 siblings, 0 replies; only message in thread
From: Patrick O'Neill @ 2023-07-31 16:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:687fce7962fb56caf1c2b3ecb4cf3dd543e4f5c6
commit r13-7667-g687fce7962fb56caf1c2b3ecb4cf3dd543e4f5c6
Author: Patrick O'Neill <patrick@rivosinc.com>
Date: Wed Apr 5 09:47:05 2023 -0700
RISC-V: Add AMO release bits
This patch sets the relevant .rl bits on amo operations.
2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Change behavior
of %A to include release bits.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Diff:
---
gcc/config/riscv/riscv.cc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 11b897aca5c..df55c427b1b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4498,8 +4498,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
break;
case 'A':
- if (riscv_memmodel_needs_amo_acquire (model))
+ if (riscv_memmodel_needs_amo_acquire (model)
+ && riscv_memmodel_needs_release_fence (model))
+ fputs (".aqrl", file);
+ else if (riscv_memmodel_needs_amo_acquire (model))
fputs (".aq", file);
+ else if (riscv_memmodel_needs_release_fence (model))
+ fputs (".rl", file);
break;
case 'F':
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