[gcc r13-7676] Daily bump.

[gcc r13-7676] Daily bump.

[GCC Administrator]

https://gcc.gnu.org/g:7ea1961dbc26b89ae8ed883d01594cedbce10e70

commit r13-7676-g7ea1961dbc26b89ae8ed883d01594cedbce10e70
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Aug 1 00:21:31 2023 +0000

    Daily bump.

Diff:
---
 gcc/ChangeLog           | 70 +++++++++++++++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |  2 +-
 gcc/m2/ChangeLog        | 15 +++++++++++
 gcc/po/ChangeLog        |  4 +++
 gcc/testsuite/ChangeLog | 44 +++++++++++++++++++++++++++++++
 libgcc/ChangeLog        |  5 ++++
 6 files changed, 139 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 24b36f7daed..c3d4a8dd3aa 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,73 @@
+2023-07-31  Martin Liska  <mliska@suse.cz>
+
+	PR target/109713
+	* config/riscv/sync.md: Add gcc_unreachable to a switch.
+
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	* config/riscv/sync.md (atomic_load<mode>): Implement atomic
+	load mapping.
+
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	* config/riscv/sync.md (mem_thread_fence_1): Change fence
+	depending on the given memory model.
+
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	* config/riscv/riscv-protos.h (riscv_union_memmodels): Expose
+	riscv_union_memmodels function to sync.md.
+	* config/riscv/riscv.cc (riscv_union_memmodels): Add function to
+	get the union of two memmodels in sync.md.
+	(riscv_print_operand): Add %I and %J flags that output the
+	optimal LR/SC flag bits for a given memory model.
+	* config/riscv/sync.md: Remove static .aqrl bits on LR op/.rl
+	bits on SC op and replace with optimized %I, %J flags.
+
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	* config/riscv/riscv.cc
+	(riscv_memmodel_needs_amo_release): Change function name.
+	(riscv_print_operand): Remove unneeded %F case.
+	* config/riscv/sync.md: Remove unneeded fences.
+
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	PR target/89835
+	* config/riscv/sync.md (atomic_store<mode>): Use simple store
+	instruction in combination with fence(s).
+
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	* config/riscv/riscv.cc (riscv_print_operand): Change behavior
+	of %A to include release bits.
+
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	* config/riscv/sync.md (atomic_cas_value_strong<mode>): Change
+	FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl
+	pair.
+
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	* config/riscv/sync.md: Change LR.aq/SC.rl pairs into
+	sequentially consistent LR.aqrl/SC.rl pairs.
+
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	* config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
+	sanitize memmodel input with memmodel_base.
+
+2023-07-31  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	Backported from master:
+	2023-06-23  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	PR tree-optimization/110280
+	* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
+	using build_vector_from_val with the element of input operand, and
+	mask's type if operand and mask's types don't match.
+
 2023-07-30  Gaius Mulley  <gaiusmod2@gmail.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index adf3b9fe518..6f43154cd32 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230731
+20230801
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index f53eafadd79..f30c8c757c4 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,18 @@
+2023-07-31  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/110284
+	* Make-lang.in: Build $(generated_files) before building
+	all $(GM2_C_OBJS).
+	(m2_OBJS): Assign $(GM2_C_OBJS).  Add m2/gm2-gcc/rtegraph.o and
+	m2/gm2-compiler-boot/m2flex.o.
+	(GM2_C_OBJS): Remove m2/stor-layout.o.
+	(m2/stor-layout.o): Remove rule.
+	* gm2-gcc/gcc-consolidation.h (rtl.h): Remove include.
+	(df.h): Remove include.
+	(except.h): Remove include.
+	(c-family/m2pp.o): Remove.
+	* Make-maintainer.in (c-family/m2pp.o): Add.
+
 2023-07-31  Gaius Mulley  <gaiusmod2@gmail.com>
 
 	Backported from master:
diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog
index 5b117959fdc..1cf2d841a2a 100644
--- a/gcc/po/ChangeLog
+++ b/gcc/po/ChangeLog
@@ -1,3 +1,7 @@
+2023-07-31  Joseph Myers  <joseph@codesourcery.com>
+
+	* sv.po: Update.
+
 2023-07-28  Joseph Myers  <joseph@codesourcery.com>
 
 	* be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 542bfd091e8..0606dddebca 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,47 @@
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	* gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test.
+	* gcc.target/riscv/amo-table-a-6-amo-add-2.c: New test.
+	* gcc.target/riscv/amo-table-a-6-amo-add-3.c: New test.
+	* gcc.target/riscv/amo-table-a-6-amo-add-4.c: New test.
+	* gcc.target/riscv/amo-table-a-6-amo-add-5.c: New test.
+	* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: New test.
+	* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: New test.
+	* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: New test.
+	* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: New test.
+	* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: New test.
+	* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: New test.
+	* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: New test.
+	* gcc.target/riscv/amo-table-a-6-fence-1.c: New test.
+	* gcc.target/riscv/amo-table-a-6-fence-2.c: New test.
+	* gcc.target/riscv/amo-table-a-6-fence-3.c: New test.
+	* gcc.target/riscv/amo-table-a-6-fence-4.c: New test.
+	* gcc.target/riscv/amo-table-a-6-fence-5.c: New test.
+	* gcc.target/riscv/amo-table-a-6-load-1.c: New test.
+	* gcc.target/riscv/amo-table-a-6-load-2.c: New test.
+	* gcc.target/riscv/amo-table-a-6-load-3.c: New test.
+	* gcc.target/riscv/amo-table-a-6-store-1.c: New test.
+	* gcc.target/riscv/amo-table-a-6-store-2.c: New test.
+	* gcc.target/riscv/amo-table-a-6-store-compat-3.c: New test.
+	* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: New test.
+	* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: New test.
+	* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: New test.
+	* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: New test.
+	* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: New test.
+
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	PR target/89835
+	* gcc.target/riscv/pr89835.c: New test.
+
+2023-07-31  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	Backported from master:
+	2023-06-23  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	PR tree-optimization/110280
+	* gcc.target/aarch64/sve/pr110280.c: New test.
+
 2023-07-31  Gaius Mulley  <gaiusmod2@gmail.com>
 
 	Backported from master:
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 7c1e6cdd609..e951b3d071b 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,8 @@
+2023-07-31  Patrick O'Neill  <patrick@rivosinc.com>
+
+	* config/riscv/atomic.c: Change LR.aq/SC.rl pairs into
+	sequentially consistent LR.aqrl/SC.rl pairs.
+
 2023-07-27  Release Manager
 
 	* GCC 13.2.0 released.