[gcc r14-4078] Daily bump.

[gcc r14-4078] Daily bump.

[GCC Administrator]

https://gcc.gnu.org/g:68845f7c4d58186cc0a5b09f7511f3c0a8f07e88

commit r14-4078-g68845f7c4d58186cc0a5b09f7511f3c0a8f07e88
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Sep 17 00:18:33 2023 +0000

    Daily bump.

Diff:
---
 gcc/ChangeLog           | 52 +++++++++++++++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |  2 +-
 gcc/testsuite/ChangeLog | 43 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 96 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 584c7d98b57..bf6c2093492 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,55 @@
+2023-09-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	PR target/111391
+	* config/riscv/autovec.md (@vec_extract<mode><vel>): Remove @.
+	(vec_extract<mode><vel>): Ditto.
+	* config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
+	(pass_vsetvl::local_eliminate_vsetvl_insn): Fix bug.
+	* config/riscv/riscv.cc (riscv_legitimize_move): Expand VLS mode to scalar mode move.
+
+2023-09-16  Tsukasa OI  <research_trasio@irq.a4lg.com>
+
+	* config/riscv/crypto.md (riscv_sha256sig0_<mode>,
+	riscv_sha256sig1_<mode>, riscv_sha256sum0_<mode>,
+	riscv_sha256sum1_<mode>, riscv_sm3p0_<mode>, riscv_sm3p1_<mode>,
+	riscv_sm4ed_<mode>, riscv_sm4ks_<mode>): Remove and replace with
+	new insn/expansions.
+	(SHA256_OP, SM3_OP, SM4_OP): New iterators.
+	(sha256_op, sm3_op, sm4_op): New attributes for iteration.
+	(*riscv_<sha256_op>_si): New raw instruction for RV32.
+	(*riscv_<sm3_op>_si): Ditto.
+	(*riscv_<sm4_op>_si): Ditto.
+	(riscv_<sha256_op>_di_extended): New base instruction for RV64.
+	(riscv_<sm3_op>_di_extended): Ditto.
+	(riscv_<sm4_op>_di_extended): Ditto.
+	(riscv_<sha256_op>_si): New common instruction expansion.
+	(riscv_<sm3_op>_si): Ditto.
+	(riscv_<sm4_op>_si): Ditto.
+	* config/riscv/riscv-builtins.cc: Add availability "crypto_zknh",
+	"crypto_zksh" and "crypto_zksed".  Remove availability
+	"crypto_zksh{32,64}" and "crypto_zksed{32,64}".
+	* config/riscv/riscv-ftypes.def: Remove unused function type.
+	* config/riscv/riscv-scalar-crypto.def: Make SHA-256, SM3 and SM4
+	intrinsics to operate on uint32_t.
+
+2023-09-16  Tsukasa OI  <research_trasio@irq.a4lg.com>
+
+	* config/riscv/riscv-builtins.cc (RISCV_ATYPE_UQI): New for
+	uint8_t.  (RISCV_ATYPE_UHI): New for uint16_t.
+	(RISCV_ATYPE_QI, RISCV_ATYPE_HI, RISCV_ATYPE_SI, RISCV_ATYPE_DI):
+	Removed as no longer used.
+	(RISCV_ATYPE_UDI): New for uint64_t.
+	* config/riscv/riscv-cmo.def: Make types unsigned for not working
+	"zicbop_cbo_prefetchi" and working bit manipulation clmul builtin
+	argument/return types.
+	* config/riscv/riscv-ftypes.def: Make bit manipulation, round
+	number and shift amount types unsigned.
+	* config/riscv/riscv-scalar-crypto.def: Ditto.
+
+2023-09-16  Pan Li  <pan2.li@intel.com>
+
+	* config/riscv/autovec-vls.md (xorsign<mode>3): New pattern.
+
 2023-09-15  Fei Gao  <gaofei@eswincomputing.com>
 
 	* config/riscv/predicates.md: Restrict predicate
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b17e44d5ded..c39a074ae51 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230916
+20230917
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 98f836493c2..97491e50ef2 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,46 @@
+2023-09-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	PR target/111391
+	* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
+	* gcc.target/riscv/rvv/autovec/pr111391-1.c: New test.
+	* gcc.target/riscv/rvv/autovec/pr111391-2.c: New test.
+
+2023-09-16  Tsukasa OI  <research_trasio@irq.a4lg.com>
+
+	* gcc.target/riscv/zknh-sha256.c: Moved to...
+	* gcc.target/riscv/zknh-sha256-64.c: ...here.  Test RV64.
+	* gcc.target/riscv/zknh-sha256-32.c: New test for RV32.
+	* gcc.target/riscv/zksh64.c: Change the type.
+	* gcc.target/riscv/zksed64.c: Ditto.
+
+2023-09-16  Tsukasa OI  <research_trasio@irq.a4lg.com>
+
+	* gcc.target/riscv/zbc32.c: Make signed type to unsigned.
+	* gcc.target/riscv/zbc64.c: Ditto.
+	* gcc.target/riscv/zbkb32.c: Ditto.
+	* gcc.target/riscv/zbkb64.c: Ditto.
+	* gcc.target/riscv/zbkc32.c: Ditto.
+	* gcc.target/riscv/zbkc64.c: Ditto.
+	* gcc.target/riscv/zbkx32.c: Ditto.
+	* gcc.target/riscv/zbkx64.c: Ditto.
+	* gcc.target/riscv/zknd32.c: Ditto.
+	* gcc.target/riscv/zknd64.c: Ditto.
+	* gcc.target/riscv/zkne32.c: Ditto.
+	* gcc.target/riscv/zkne64.c: Ditto.
+	* gcc.target/riscv/zknh-sha256.c: Ditto.
+	* gcc.target/riscv/zknh-sha512-32.c: Ditto.
+	* gcc.target/riscv/zknh-sha512-64.c: Ditto.
+	* gcc.target/riscv/zksed32.c: Ditto.
+	* gcc.target/riscv/zksed64.c: Ditto.
+	* gcc.target/riscv/zksh32.c: Ditto.
+	* gcc.target/riscv/zksh64.c: Ditto.
+
+2023-09-16  Pan Li  <pan2.li@intel.com>
+
+	* gcc.target/riscv/rvv/autovec/vls/def.h: New macro.
+	* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c: New test.
+	* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: New test.
+
 2023-09-15  David Malcolm  <dmalcolm@redhat.com>
 
 	* c-c++-common/analyzer/volatile-1.c: New test.