[gcc r14-4079] rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index

[gcc r14-4079] rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index

[Ajit Kumar Agarwal]

https://gcc.gnu.org/g:b34f8e705d961260adc2bea95db4361b2e70d565

commit r14-4079-gb34f8e705d961260adc2bea95db4361b2e70d565
Author: Ajit Kumar Agarwal <aagarwa1@linux.ibm.com>
Date:   Sun Sep 17 12:27:10 2023 -0500

    rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index
    
    For rs6000 target we dont need zero_extend after vctzlsbb as vctzlsbb
    already zero extend.
    
    2023-09-17  Ajit Kumar Agarwal  <aagarwa1@linux.ibm.com>
    
    gcc/ChangeLog:
    
            * config/rs6000/vsx.md (*vctzlsbb_zext_<mode>): New define_insn.
    
    gcc/testsuite/ChangeLog:
    
            * g++.target/powerpc/altivec-19.C: New testcase.

Diff:
---
 gcc/config/rs6000/vsx.md                      | 17 ++++++++++++++---
 gcc/testsuite/g++.target/powerpc/altivec-19.C | 10 ++++++++++
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 19abfeb565a..4de41e78d51 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5846,11 +5846,22 @@
   [(set_attr "type" "vecsimple")])
 
 ;; Vector Count Trailing Zero Least-Significant Bits Byte
-(define_insn "vctzlsbb_<mode>"
-  [(set (match_operand:SI 0 "register_operand" "=r")
+(define_insn "*vctzlsbb_zext_<mode>"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI
 	(unspec:SI
 	 [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
-	 UNSPEC_VCTZLSBB))]
+	 UNSPEC_VCTZLSBB)))]
+  "TARGET_P9_VECTOR"
+  "vctzlsbb %0,%1"
+  [(set_attr "type" "vecsimple")])
+
+;; Vector Count Trailing Zero Least-Significant Bits Byte
+(define_insn "vctzlsbb_<mode>"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI
+         [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
+         UNSPEC_VCTZLSBB))]
   "TARGET_P9_VECTOR"
   "vctzlsbb %0,%1"
   [(set_attr "type" "vecsimple")])
diff --git a/gcc/testsuite/g++.target/powerpc/altivec-19.C b/gcc/testsuite/g++.target/powerpc/altivec-19.C
new file mode 100644
index 00000000000..5879e72dfd2
--- /dev/null
+++ b/gcc/testsuite/g++.target/powerpc/altivec-19.C
@@ -0,0 +1,10 @@
+/* { dg-do compile } */ 
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2 " } */ 
+
+#include <altivec.h>
+
+unsigned int foo (vector unsigned char a, vector unsigned char b) {
+  return vec_first_match_or_eos_index (a, b);
+}
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */