[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Bugfix PR111362 for incorrect frm emit

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Bugfix PR111362 for incorrect frm emit

[Jeff Law]

https://gcc.gnu.org/g:bb9581bef49ea149addbd8d46fee13c389a5d823

commit bb9581bef49ea149addbd8d46fee13c389a5d823
Author: Pan Li <pan2.li@intel.com>
Date:   Wed Sep 13 11:34:42 2023 +0800

    RISC-V: Bugfix PR111362 for incorrect frm emit
    
    When the mode switching from NONE to CALL, we will restore the
    frm but lack some check if we have static frm insn in cfun.
    
    This patch would like to fix this by adding static frm insn check.
    
            PR target/111362
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.cc (riscv_emit_frm_mode_set): Bugfix.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/no-honor-frm-1.c: New test.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    (cherry picked from commit feb23a37e6142016c3463aa3be3e900d45bc3ea5)

Diff:
---
 gcc/config/riscv/riscv.cc                                |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 9d04ddd69e0..762937b0e37 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9173,7 +9173,7 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
       rtx frm = gen_int_mode (mode, SImode);
 
       if (mode == riscv_vector::FRM_DYN_CALL
-	&& prev_mode != riscv_vector::FRM_DYN)
+	&& prev_mode != riscv_vector::FRM_DYN && STATIC_FRM_P (cfun))
 	/* No need to emit when prev mode is DYN already.  */
 	emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
       else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
new file mode 100644
index 00000000000..b2e0f217bfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+void foo (void) {
+  for (unsigned i = 0; i < sizeof(foo); i++)
+    __builtin_printf("%d", i);
+}
+
+/* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */
+/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */
+/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */