[gcc(refs/users/meissner/heads/work134-vsize)] Adjust vector pair split functions.

[gcc(refs/users/meissner/heads/work134-vsize)] Adjust vector pair split functions.

[Michael Meissner]

https://gcc.gnu.org/g:92cc5d27106c7389ba98a137a8699eef5a6382bb

commit 92cc5d27106c7389ba98a137a8699eef5a6382bb
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Sep 25 13:03:36 2023 -0400

    Adjust vector pair split functions.
    
    2023-09-21  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.cc (split_unary_vector_pair): Add code to allow
            split to be done before register allocation time.
            (split_binary_vector_pair): Likewise.
            (split_fma_vector_pair): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 65 +++++++++++++++++++++++++--------------------
 1 file changed, 36 insertions(+), 29 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 33efbcee9af..37444f4eafc 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -27404,15 +27404,17 @@ split_unary_vector_pair (machine_mode mode,		/* vector mode.  */
 			 rtx operands[],		/* dest, src.  */
 			 rtx (*func)(rtx, rtx))		/* create insn.  */
 {
-  unsigned reg0 = reg_or_subregno (operands[0]);
-  unsigned reg1 = reg_or_subregno (operands[1]);
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  machine_mode orig_mode = GET_MODE (op0);
 
-  emit_insn (func (gen_rtx_REG (mode, reg0),
-		   gen_rtx_REG (mode, reg1)));
-
-  emit_insn (func (gen_rtx_REG (mode, reg0 + 1),
-		   gen_rtx_REG (mode, reg1 + 1)));
+  rtx reg0_vector0 = simplify_gen_subreg (mode, op0, orig_mode, 0);
+  rtx reg1_vector0 = simplify_gen_subreg (mode, op1, orig_mode, 0);
+  rtx reg0_vector1 = simplify_gen_subreg (mode, op0, orig_mode, 16);
+  rtx reg1_vector1 = simplify_gen_subreg (mode, op1, orig_mode, 16);
 
+  emit_insn (func (reg0_vector0, reg1_vector0));
+  emit_insn (func (reg0_vector1, reg1_vector1));
   return;
 }
 
@@ -27423,18 +27425,20 @@ split_binary_vector_pair (machine_mode mode,		/* vector mode.  */
 			 rtx operands[],		/* dest, src.  */
 			 rtx (*func)(rtx, rtx, rtx))	/* create insn.  */
 {
-  unsigned reg0 = reg_or_subregno (operands[0]);
-  unsigned reg1 = reg_or_subregno (operands[1]);
-  unsigned reg2 = reg_or_subregno (operands[2]);
-
-  emit_insn (func (gen_rtx_REG (mode, reg0),
-		   gen_rtx_REG (mode, reg1),
-		   gen_rtx_REG (mode, reg2)));
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  rtx op2 = operands[2];
+  machine_mode orig_mode = GET_MODE (op0);
 
-  emit_insn (func (gen_rtx_REG (mode, reg0 + 1),
-		   gen_rtx_REG (mode, reg1 + 1),
-		   gen_rtx_REG (mode, reg2 + 1)));
+  rtx reg0_vector0 = simplify_gen_subreg (mode, op0, orig_mode, 0);
+  rtx reg1_vector0 = simplify_gen_subreg (mode, op1, orig_mode, 0);
+  rtx reg2_vector0 = simplify_gen_subreg (mode, op2, orig_mode, 0);
+  rtx reg0_vector1 = simplify_gen_subreg (mode, op0, orig_mode, 16);
+  rtx reg1_vector1 = simplify_gen_subreg (mode, op1, orig_mode, 16);
+  rtx reg2_vector1 = simplify_gen_subreg (mode, op2, orig_mode, 16);
 
+  emit_insn (func (reg0_vector0, reg1_vector0, reg2_vector0));
+  emit_insn (func (reg0_vector1, reg1_vector1, reg2_vector1));
   return;
 }
 
@@ -27446,21 +27450,24 @@ split_fma_vector_pair (machine_mode mode,		/* vector mode.  */
 		       rtx operands[],			/* dest, src.  */
 		       rtx (*func)(rtx, rtx, rtx, rtx))	/* create insn.  */
 {
-  unsigned reg0 = reg_or_subregno (operands[0]);
-  unsigned reg1 = reg_or_subregno (operands[1]);
-  unsigned reg2 = reg_or_subregno (operands[2]);
-  unsigned reg3 = reg_or_subregno (operands[3]);
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  rtx op2 = operands[2];
+  rtx op3 = operands[3];
+  machine_mode orig_mode = GET_MODE (op0);
 
-  emit_insn (func (gen_rtx_REG (mode, reg0),
-		   gen_rtx_REG (mode, reg1),
-		   gen_rtx_REG (mode, reg2),
-		   gen_rtx_REG (mode, reg3)));
+  rtx reg0_vector0 = simplify_gen_subreg (mode, op0, orig_mode, 0);
+  rtx reg1_vector0 = simplify_gen_subreg (mode, op1, orig_mode, 0);
+  rtx reg2_vector0 = simplify_gen_subreg (mode, op2, orig_mode, 0);
+  rtx reg3_vector0 = simplify_gen_subreg (mode, op3, orig_mode, 0);
 
-  emit_insn (func (gen_rtx_REG (mode, reg0 + 1),
-		   gen_rtx_REG (mode, reg1 + 1),
-		   gen_rtx_REG (mode, reg2 + 1),
-		   gen_rtx_REG (mode, reg3 + 1)));
+  rtx reg0_vector1 = simplify_gen_subreg (mode, op0, orig_mode, 16);
+  rtx reg1_vector1 = simplify_gen_subreg (mode, op1, orig_mode, 16);
+  rtx reg2_vector1 = simplify_gen_subreg (mode, op2, orig_mode, 16);
+  rtx reg3_vector1 = simplify_gen_subreg (mode, op3, orig_mode, 16);
 
+  emit_insn (func (reg0_vector0, reg1_vector0, reg2_vector0, reg3_vector0));
+  emit_insn (func (reg0_vector1, reg1_vector1, reg2_vector1, reg3_vector1));
   return;
 }