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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Support VLS mult high
@ 2023-09-26 15:11 Jeff Law
0 siblings, 0 replies; only message in thread
From: Jeff Law @ 2023-09-26 15:11 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:da973da366cba2e725749277b554f3c3f211f54e
commit da973da366cba2e725749277b554f3c3f211f54e
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Thu Sep 21 19:54:10 2023 +0800
RISC-V: Support VLS mult high
Regression passed.
Committed.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Extend VLS modes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mult high.
* gcc.target/riscv/rvv/autovec/vls/mulh-1.c: New test.
(cherry picked from commit 94982a6b9cf4c61357eabebd14866969ef4c2b6e)
Diff:
---
gcc/config/riscv/vector-iterators.md | 47 ++++++++++
.../gcc.target/riscv/rvv/autovec/vls/def.h | 8 ++
.../gcc.target/riscv/rvv/autovec/vls/mulh-1.c | 104 +++++++++++++++++++++
3 files changed, 159 insertions(+)
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 5c4b433c6bf..4aa64127df7 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -670,6 +670,53 @@
RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
(RVVM8DI "TARGET_FULL_V") (RVVM4DI "TARGET_FULL_V") (RVVM2DI "TARGET_FULL_V") (RVVM1DI "TARGET_FULL_V")
+
+ (V1QI "TARGET_VECTOR_VLS")
+ (V2QI "TARGET_VECTOR_VLS")
+ (V4QI "TARGET_VECTOR_VLS")
+ (V8QI "TARGET_VECTOR_VLS")
+ (V16QI "TARGET_VECTOR_VLS")
+ (V32QI "TARGET_VECTOR_VLS")
+ (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+ (V1HI "TARGET_VECTOR_VLS")
+ (V2HI "TARGET_VECTOR_VLS")
+ (V4HI "TARGET_VECTOR_VLS")
+ (V8HI "TARGET_VECTOR_VLS")
+ (V16HI "TARGET_VECTOR_VLS")
+ (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+ (V1SI "TARGET_VECTOR_VLS")
+ (V2SI "TARGET_VECTOR_VLS")
+ (V4SI "TARGET_VECTOR_VLS")
+ (V8SI "TARGET_VECTOR_VLS")
+ (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+ (V1DI "TARGET_VECTOR_VLS && TARGET_FULL_V")
+ (V2DI "TARGET_VECTOR_VLS && TARGET_FULL_V")
+ (V4DI "TARGET_VECTOR_VLS && TARGET_FULL_V")
+ (V8DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 64")
+ (V16DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 128")
+ (V32DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 256")
+ (V64DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 512")
+ (V128DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 1024")
+ (V256DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 2048")
+ (V512DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 4096")
])
(define_mode_iterator VI_QH [
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 74685f8d05e..26671b2975c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -518,3 +518,11 @@ typedef double v512df __attribute__ ((vector_size (4096)));
for (int i = 0; i < NUM; i++) \
dst[i] = ((TYPE2) a[i] + b[i] + 1) >> 1; \
}
+
+#define DEF_MULH(TYPE, NUM) \
+ void __attribute__ ((noipa)) \
+ mod_##TYPE##_##NUM (TYPE *__restrict dst, TYPE *__restrict src) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ dst[i] = src[i] % 19; \
+ }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c
new file mode 100644
index 00000000000..47bb40f9828
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_MULH (int8_t, 4)
+DEF_MULH (int8_t, 8)
+DEF_MULH (int8_t, 16)
+DEF_MULH (int8_t, 32)
+DEF_MULH (int8_t, 64)
+DEF_MULH (int8_t, 128)
+DEF_MULH (int8_t, 256)
+DEF_MULH (int8_t, 512)
+DEF_MULH (int8_t, 1024)
+DEF_MULH (int8_t, 2048)
+DEF_MULH (int8_t, 4096)
+
+DEF_MULH (int16_t, 4)
+DEF_MULH (int16_t, 8)
+DEF_MULH (int16_t, 16)
+DEF_MULH (int16_t, 32)
+DEF_MULH (int16_t, 64)
+DEF_MULH (int16_t, 128)
+DEF_MULH (int16_t, 256)
+DEF_MULH (int16_t, 512)
+DEF_MULH (int16_t, 1024)
+DEF_MULH (int16_t, 2048)
+
+DEF_MULH (int32_t, 4)
+DEF_MULH (int32_t, 8)
+DEF_MULH (int32_t, 16)
+DEF_MULH (int32_t, 32)
+DEF_MULH (int32_t, 64)
+DEF_MULH (int32_t, 128)
+DEF_MULH (int32_t, 256)
+DEF_MULH (int32_t, 512)
+DEF_MULH (int32_t, 1024)
+
+DEF_MULH (int64_t, 4)
+DEF_MULH (int64_t, 8)
+DEF_MULH (int64_t, 16)
+DEF_MULH (int64_t, 32)
+DEF_MULH (int64_t, 64)
+DEF_MULH (int64_t, 128)
+DEF_MULH (int64_t, 256)
+DEF_MULH (int64_t, 512)
+
+DEF_MULH (uint8_t, 4)
+DEF_MULH (uint8_t, 8)
+DEF_MULH (uint8_t, 16)
+DEF_MULH (uint8_t, 32)
+DEF_MULH (uint8_t, 64)
+DEF_MULH (uint8_t, 128)
+DEF_MULH (uint8_t, 256)
+DEF_MULH (uint8_t, 512)
+DEF_MULH (uint8_t, 1024)
+DEF_MULH (uint8_t, 2048)
+DEF_MULH (uint8_t, 4096)
+
+DEF_MULH (uint16_t, 4)
+DEF_MULH (uint16_t, 8)
+DEF_MULH (uint16_t, 16)
+DEF_MULH (uint16_t, 32)
+DEF_MULH (uint16_t, 64)
+DEF_MULH (uint16_t, 128)
+DEF_MULH (uint16_t, 256)
+DEF_MULH (uint16_t, 512)
+DEF_MULH (uint16_t, 1024)
+DEF_MULH (uint16_t, 2048)
+
+DEF_MULH (uint32_t, 4)
+DEF_MULH (uint32_t, 8)
+DEF_MULH (uint32_t, 16)
+DEF_MULH (uint32_t, 32)
+DEF_MULH (uint32_t, 64)
+DEF_MULH (uint32_t, 128)
+DEF_MULH (uint32_t, 256)
+DEF_MULH (uint32_t, 512)
+DEF_MULH (uint32_t, 1024)
+
+DEF_MULH (uint64_t, 4)
+DEF_MULH (uint64_t, 8)
+DEF_MULH (uint64_t, 16)
+DEF_MULH (uint64_t, 32)
+DEF_MULH (uint64_t, 64)
+DEF_MULH (uint64_t, 128)
+DEF_MULH (uint64_t, 256)
+DEF_MULH (uint64_t, 512)
+
+/* { dg-final { scan-assembler-times {vmulh\.} 38 } } */
+/* { dg-final { scan-assembler-times {vmulhu\.} 38 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
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