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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add VLS conditional patterns support
@ 2023-09-26 15:12 Jeff Law
0 siblings, 0 replies; only message in thread
From: Jeff Law @ 2023-09-26 15:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7f62d9867bb85d995d4ff7764827e76e5dbc730a
commit 7f62d9867bb85d995d4ff7764827e76e5dbc730a
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Fri Sep 22 11:44:49 2023 +0800
RISC-V: Add VLS conditional patterns support
Regression passed.
Committed.
gcc/ChangeLog:
* config/riscv/autovec.md: Add VLS conditional patterns.
* config/riscv/riscv-protos.h (expand_cond_unop): Ditto.
(expand_cond_binop): Ditto.
(expand_cond_ternop): Ditto.
* config/riscv/riscv-v.cc (expand_cond_unop): Ditto.
(expand_cond_binop): Ditto.
(expand_cond_ternop): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS conditional tests.
* gcc.target/riscv/rvv/autovec/vls/cond_add-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_add-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_and-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_div-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_div-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_max-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_max-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_min-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_min-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_not-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c: New test.
(cherry picked from commit 8a87ba0b4fe72acbf34e48898652d0f78b9e235e)
Diff:
---
gcc/config/riscv/autovec.md | 200 +++++++++------------
gcc/config/riscv/riscv-protos.h | 3 +
gcc/config/riscv/riscv-v.cc | 45 +++++
.../gcc.target/riscv/rvv/autovec/vls/cond_add-1.c | 104 +++++++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_add-2.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_and-1.c | 104 +++++++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_div-1.c | 58 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_div-2.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c | 62 +++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c | 62 +++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c | 104 +++++++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_max-1.c | 104 +++++++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_max-2.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_min-1.c | 104 +++++++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_min-2.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c | 58 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c | 104 +++++++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c | 62 +++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_not-1.c | 62 +++++++
.../riscv/rvv/autovec/vls/cond_shift-1.c | 57 ++++++
.../riscv/rvv/autovec/vls/cond_shift-2.c | 56 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c | 104 +++++++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c | 50 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c | 104 +++++++++++
.../gcc.target/riscv/rvv/autovec/vls/def.h | 70 ++++++++
31 files changed, 2059 insertions(+), 118 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index b92cb7a5d0f..6f35fb1bd9e 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1492,18 +1492,15 @@
;; -------------------------------------------------------------------------
(define_expand "cond_<optab><mode>"
- [(match_operand:VI 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_int_unop:VI
- (match_operand:VI 2 "register_operand"))
- (match_operand:VI 3 "autovec_else_operand")]
+ (any_int_unop:V_VLSI
+ (match_operand:V_VLSI 2 "register_operand"))
+ (match_operand:V_VLSI 3 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2],
- operands[3],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_unop (icode, operands);
DONE;
})
@@ -1530,18 +1527,15 @@
;; -------------------------------------------------------------------------
(define_expand "cond_<optab><mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_float_unop_nofrm:VF
- (match_operand:VF 2 "register_operand"))
- (match_operand:VF 3 "autovec_else_operand")]
+ (any_float_unop_nofrm:V_VLSF
+ (match_operand:V_VLSF 2 "register_operand"))
+ (match_operand:V_VLSF 3 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2],
- operands[3],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_unop (icode, operands);
DONE;
})
@@ -1568,19 +1562,16 @@
;; -------------------------------------------------------------------------
(define_expand "cond_<optab><mode>"
- [(match_operand:VI 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_shift:VI
- (match_operand:VI 2 "register_operand")
- (match_operand:VI 3 "vector_shift_operand"))
- (match_operand:VI 4 "autovec_else_operand")]
+ (any_shift:V_VLSI
+ (match_operand:V_VLSI 2 "register_operand")
+ (match_operand:V_VLSI 3 "vector_shift_operand"))
+ (match_operand:V_VLSI 4 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2],
- operands[3], operands[4],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_binop (icode, operands);
DONE;
})
@@ -1609,19 +1600,16 @@
;; -------------------------------------------------------------------------
(define_expand "cond_<optab><mode>"
- [(match_operand:VI 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_int_binop_no_shift:VI
- (match_operand:VI 2 "<binop_rhs1_predicate>")
- (match_operand:VI 3 "<binop_rhs2_predicate>"))
- (match_operand:VI 4 "autovec_else_operand")]
+ (any_int_binop_no_shift:V_VLSI
+ (match_operand:V_VLSI 2 "<binop_rhs1_predicate>")
+ (match_operand:V_VLSI 3 "<binop_rhs2_predicate>"))
+ (match_operand:V_VLSI 4 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2],
- operands[3], operands[4],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_binop (icode, operands);
DONE;
})
@@ -1650,19 +1638,16 @@
;; -------------------------------------------------------------------------
(define_expand "cond_<optab><mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_float_binop:VF
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand"))
- (match_operand:VF 4 "autovec_else_operand")]
+ (any_float_binop:V_VLSF
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand"))
+ (match_operand:V_VLSF 4 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2],
- operands[3], operands[4],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_binop (icode, operands);
DONE;
})
@@ -1689,19 +1674,16 @@
;; -------------------------------------------------------------------------
(define_expand "cond_<optab><mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_float_binop_nofrm:VF
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand"))
- (match_operand:VF 4 "autovec_else_operand")]
+ (any_float_binop_nofrm:V_VLSF
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand"))
+ (match_operand:V_VLSF 4 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2],
- operands[3], operands[4],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_binop (icode, operands);
DONE;
})
@@ -1729,19 +1711,16 @@
;; -------------------------------------------------------------------------
(define_expand "cond_fma<mode>"
- [(match_operand:VI 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VI 2 "register_operand")
- (match_operand:VI 3 "register_operand")
- (match_operand:VI 4 "register_operand")
- (match_operand:VI 5 "autovec_else_operand")]
+ (match_operand:V_VLSI 2 "register_operand")
+ (match_operand:V_VLSI 3 "register_operand")
+ (match_operand:V_VLSI 4 "register_operand")
+ (match_operand:V_VLSI 5 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_fma<mode> (operands[0], operands[1], operands[2],
- operands[3], operands[4], operands[5],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred_mul_plus (<MODE>mode);
+ riscv_vector::expand_cond_ternop (icode, operands);
DONE;
})
@@ -1762,19 +1741,16 @@
})
(define_expand "cond_fnma<mode>"
- [(match_operand:VI 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VI 2 "register_operand")
- (match_operand:VI 3 "register_operand")
- (match_operand:VI 4 "register_operand")
- (match_operand:VI 5 "autovec_else_operand")]
+ (match_operand:V_VLSI 2 "register_operand")
+ (match_operand:V_VLSI 3 "register_operand")
+ (match_operand:V_VLSI 4 "register_operand")
+ (match_operand:V_VLSI 5 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_fnma<mode> (operands[0], operands[1], operands[2],
- operands[3], operands[4], operands[5],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred_minus_mul (<MODE>mode);
+ riscv_vector::expand_cond_ternop (icode, operands);
DONE;
})
@@ -1802,19 +1778,16 @@
;; -------------------------------------------------------------------------
(define_expand "cond_fma<mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")
- (match_operand:VF 4 "register_operand")
- (match_operand:VF 5 "autovec_else_operand")]
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")
+ (match_operand:V_VLSF 4 "register_operand")
+ (match_operand:V_VLSF 5 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_fma<mode> (operands[0], operands[1], operands[2],
- operands[3], operands[4], operands[5],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred_mul (PLUS, <MODE>mode);
+ riscv_vector::expand_cond_ternop (icode, operands);
DONE;
})
@@ -1835,19 +1808,16 @@
})
(define_expand "cond_fnma<mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")
- (match_operand:VF 4 "register_operand")
- (match_operand:VF 5 "autovec_else_operand")]
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")
+ (match_operand:V_VLSF 4 "register_operand")
+ (match_operand:V_VLSF 5 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_fnma<mode> (operands[0], operands[1], operands[2],
- operands[3], operands[4], operands[5],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred_mul_neg (PLUS, <MODE>mode);
+ riscv_vector::expand_cond_ternop (icode, operands);
DONE;
})
@@ -1868,19 +1838,16 @@
})
(define_expand "cond_fms<mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")
- (match_operand:VF 4 "register_operand")
- (match_operand:VF 5 "autovec_else_operand")]
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")
+ (match_operand:V_VLSF 4 "register_operand")
+ (match_operand:V_VLSF 5 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_fms<mode> (operands[0], operands[1], operands[2],
- operands[3], operands[4], operands[5],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred_mul (MINUS, <MODE>mode);
+ riscv_vector::expand_cond_ternop (icode, operands);
DONE;
})
@@ -1901,19 +1868,16 @@
})
(define_expand "cond_fnms<mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")
- (match_operand:VF 4 "register_operand")
- (match_operand:VF 5 "autovec_else_operand")]
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")
+ (match_operand:V_VLSF 4 "register_operand")
+ (match_operand:V_VLSF 5 "autovec_else_operand")]
"TARGET_VECTOR"
{
- /* Normalize into cond_len_* operations. */
- emit_insn (gen_cond_len_fnms<mode> (operands[0], operands[1], operands[2],
- operands[3], operands[4], operands[5],
- gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
- const0_rtx));
+ insn_code icode = code_for_pred_mul_neg (MINUS, <MODE>mode);
+ riscv_vector::expand_cond_ternop (icode, operands);
DONE;
})
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 3eec72b6703..34becfbaba8 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -485,6 +485,9 @@ void expand_cond_len_ternop (unsigned, rtx *);
void prepare_ternary_operands (rtx *);
void expand_lanes_load_store (rtx *, bool);
void expand_fold_extract_last (rtx *);
+void expand_cond_unop (unsigned, rtx *);
+void expand_cond_binop (unsigned, rtx *);
+void expand_cond_ternop (unsigned, rtx *);
/* Rounding mode bitfield for fixed point VXRM. */
enum fixed_point_rounding_mode
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 8379491c9ab..a3672bad521 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -3061,6 +3061,20 @@ expand_cond_len_unop (unsigned icode, rtx *ops)
expand_cond_len_op (icode, UNARY_OP_P, cond_ops, len);
}
+/* Expand unary ops COND_*. */
+void
+expand_cond_unop (unsigned icode, rtx *ops)
+{
+ rtx dest = ops[0];
+ rtx mask = ops[1];
+ rtx src = ops[2];
+ rtx merge = get_else_operand (ops[3]);
+ rtx len = gen_int_mode (GET_MODE_NUNITS (GET_MODE (dest)), Pmode);
+
+ rtx cond_ops[] = {dest, mask, merge, src};
+ expand_cond_len_op (icode, UNARY_OP_P, cond_ops, len);
+}
+
/* Expand binary ops COND_LEN_*. */
void
expand_cond_len_binop (unsigned icode, rtx *ops)
@@ -3076,6 +3090,21 @@ expand_cond_len_binop (unsigned icode, rtx *ops)
expand_cond_len_op (icode, BINARY_OP_P, cond_ops, len);
}
+/* Expand binary ops COND_*. */
+void
+expand_cond_binop (unsigned icode, rtx *ops)
+{
+ rtx dest = ops[0];
+ rtx mask = ops[1];
+ rtx src1 = ops[2];
+ rtx src2 = ops[3];
+ rtx merge = get_else_operand (ops[4]);
+ rtx len = gen_int_mode (GET_MODE_NUNITS (GET_MODE (dest)), Pmode);
+
+ rtx cond_ops[] = {dest, mask, merge, src1, src2};
+ expand_cond_len_op (icode, BINARY_OP_P, cond_ops, len);
+}
+
/* Prepare insn_code for gather_load/scatter_store according to
the vector mode and index mode. */
static insn_code
@@ -3248,6 +3277,22 @@ expand_cond_len_ternop (unsigned icode, rtx *ops)
expand_cond_len_op (icode, TERNARY_OP_P, cond_ops, len);
}
+/* Expand COND_*. */
+void
+expand_cond_ternop (unsigned icode, rtx *ops)
+{
+ rtx dest = ops[0];
+ rtx mask = ops[1];
+ rtx src1 = ops[2];
+ rtx src2 = ops[3];
+ rtx src3 = ops[4];
+ rtx merge = get_else_operand (ops[5]);
+ rtx len = gen_int_mode (GET_MODE_NUNITS (GET_MODE (dest)), Pmode);
+
+ rtx cond_ops[] = {dest, mask, src1, src2, src3, merge};
+ expand_cond_len_op (icode, TERNARY_OP_P, cond_ops, len);
+}
+
/* Expand reduction operations.
Case 1: ops = {scalar_dest, vector_src}
Case 2: ops = {scalar_dest, vector_src, mask, vl}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c
new file mode 100644
index 00000000000..61da94cbc41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_add, 4, v4qi, +)
+DEF_COND_BINOP (cond_add, 8, v8qi, +)
+DEF_COND_BINOP (cond_add, 16, v16qi, +)
+DEF_COND_BINOP (cond_add, 32, v32qi, +)
+DEF_COND_BINOP (cond_add, 64, v64qi, +)
+DEF_COND_BINOP (cond_add, 128, v128qi, +)
+DEF_COND_BINOP (cond_add, 256, v256qi, +)
+DEF_COND_BINOP (cond_add, 512, v512qi, +)
+DEF_COND_BINOP (cond_add, 1024, v1024qi, +)
+DEF_COND_BINOP (cond_add, 2048, v2048qi, +)
+DEF_COND_BINOP (cond_add, 4096, v4096qi, +)
+
+DEF_COND_BINOP (cond_add, 4, v4hi, +)
+DEF_COND_BINOP (cond_add, 8, v8hi, +)
+DEF_COND_BINOP (cond_add, 16, v16hi, +)
+DEF_COND_BINOP (cond_add, 32, v32hi, +)
+DEF_COND_BINOP (cond_add, 64, v64hi, +)
+DEF_COND_BINOP (cond_add, 128, v128hi, +)
+DEF_COND_BINOP (cond_add, 256, v256hi, +)
+DEF_COND_BINOP (cond_add, 512, v512hi, +)
+DEF_COND_BINOP (cond_add, 1024, v1024hi, +)
+DEF_COND_BINOP (cond_add, 2048, v2048hi, +)
+
+DEF_COND_BINOP (cond_add, 4, v4si, +)
+DEF_COND_BINOP (cond_add, 8, v8si, +)
+DEF_COND_BINOP (cond_add, 16, v16si, +)
+DEF_COND_BINOP (cond_add, 32, v32si, +)
+DEF_COND_BINOP (cond_add, 64, v64si, +)
+DEF_COND_BINOP (cond_add, 128, v128si, +)
+DEF_COND_BINOP (cond_add, 256, v256si, +)
+DEF_COND_BINOP (cond_add, 512, v512si, +)
+DEF_COND_BINOP (cond_add, 1024, v1024si, +)
+
+DEF_COND_BINOP (cond_add, 4, v4di, +)
+DEF_COND_BINOP (cond_add, 8, v8di, +)
+DEF_COND_BINOP (cond_add, 16, v16di, +)
+DEF_COND_BINOP (cond_add, 32, v32di, +)
+DEF_COND_BINOP (cond_add, 64, v64di, +)
+DEF_COND_BINOP (cond_add, 128, v128di, +)
+DEF_COND_BINOP (cond_add, 256, v256di, +)
+DEF_COND_BINOP (cond_add, 512, v512di, +)
+
+DEF_COND_BINOP (cond_add, 4, v4uqi, +)
+DEF_COND_BINOP (cond_add, 8, v8uqi, +)
+DEF_COND_BINOP (cond_add, 16, v16uqi, +)
+DEF_COND_BINOP (cond_add, 32, v32uqi, +)
+DEF_COND_BINOP (cond_add, 64, v64uqi, +)
+DEF_COND_BINOP (cond_add, 128, v128uqi, +)
+DEF_COND_BINOP (cond_add, 256, v256uqi, +)
+DEF_COND_BINOP (cond_add, 512, v512uqi, +)
+DEF_COND_BINOP (cond_add, 1024, v1024uqi, +)
+DEF_COND_BINOP (cond_add, 2048, v2048uqi, +)
+DEF_COND_BINOP (cond_add, 4096, v4096uqi, +)
+
+DEF_COND_BINOP (cond_add, 4, v4uhi, +)
+DEF_COND_BINOP (cond_add, 8, v8uhi, +)
+DEF_COND_BINOP (cond_add, 16, v16uhi, +)
+DEF_COND_BINOP (cond_add, 32, v32uhi, +)
+DEF_COND_BINOP (cond_add, 64, v64uhi, +)
+DEF_COND_BINOP (cond_add, 128, v128uhi, +)
+DEF_COND_BINOP (cond_add, 256, v256uhi, +)
+DEF_COND_BINOP (cond_add, 512, v512uhi, +)
+DEF_COND_BINOP (cond_add, 1024, v1024uhi, +)
+DEF_COND_BINOP (cond_add, 2048, v2048uhi, +)
+
+DEF_COND_BINOP (cond_add, 4, v4usi, +)
+DEF_COND_BINOP (cond_add, 8, v8usi, +)
+DEF_COND_BINOP (cond_add, 16, v16usi, +)
+DEF_COND_BINOP (cond_add, 32, v32usi, +)
+DEF_COND_BINOP (cond_add, 64, v64usi, +)
+DEF_COND_BINOP (cond_add, 128, v128usi, +)
+DEF_COND_BINOP (cond_add, 256, v256usi, +)
+DEF_COND_BINOP (cond_add, 512, v512usi, +)
+DEF_COND_BINOP (cond_add, 1024, v1024usi, +)
+
+DEF_COND_BINOP (cond_add, 4, v4udi, +)
+DEF_COND_BINOP (cond_add, 8, v8udi, +)
+DEF_COND_BINOP (cond_add, 16, v16udi, +)
+DEF_COND_BINOP (cond_add, 32, v32udi, +)
+DEF_COND_BINOP (cond_add, 64, v64udi, +)
+DEF_COND_BINOP (cond_add, 128, v128udi, +)
+DEF_COND_BINOP (cond_add, 256, v256udi, +)
+DEF_COND_BINOP (cond_add, 512, v512udi, +)
+
+/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c
new file mode 100644
index 00000000000..cb730870211
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_add, 4, v4hf, +)
+DEF_COND_BINOP (cond_add, 8, v8hf, +)
+DEF_COND_BINOP (cond_add, 16, v16hf, +)
+DEF_COND_BINOP (cond_add, 32, v32hf, +)
+DEF_COND_BINOP (cond_add, 64, v64hf, +)
+DEF_COND_BINOP (cond_add, 128, v128hf, +)
+DEF_COND_BINOP (cond_add, 256, v256hf, +)
+DEF_COND_BINOP (cond_add, 512, v512hf, +)
+DEF_COND_BINOP (cond_add, 1024, v1024hf, +)
+DEF_COND_BINOP (cond_add, 2048, v2048hf, +)
+
+DEF_COND_BINOP (cond_add, 4, v4sf, +)
+DEF_COND_BINOP (cond_add, 8, v8sf, +)
+DEF_COND_BINOP (cond_add, 16, v16sf, +)
+DEF_COND_BINOP (cond_add, 32, v32sf, +)
+DEF_COND_BINOP (cond_add, 64, v64sf, +)
+DEF_COND_BINOP (cond_add, 128, v128sf, +)
+DEF_COND_BINOP (cond_add, 256, v256sf, +)
+DEF_COND_BINOP (cond_add, 512, v512sf, +)
+DEF_COND_BINOP (cond_add, 1024, v1024sf, +)
+
+DEF_COND_BINOP (cond_add, 4, v4df, +)
+DEF_COND_BINOP (cond_add, 8, v8df, +)
+DEF_COND_BINOP (cond_add, 16, v16df, +)
+DEF_COND_BINOP (cond_add, 32, v32df, +)
+DEF_COND_BINOP (cond_add, 64, v64df, +)
+DEF_COND_BINOP (cond_add, 128, v128df, +)
+DEF_COND_BINOP (cond_add, 256, v256df, +)
+DEF_COND_BINOP (cond_add, 512, v512df, +)
+
+/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c
new file mode 100644
index 00000000000..eb8d56a2a1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_and, 4, v4qi, &)
+DEF_COND_BINOP (cond_and, 8, v8qi, &)
+DEF_COND_BINOP (cond_and, 16, v16qi, &)
+DEF_COND_BINOP (cond_and, 32, v32qi, &)
+DEF_COND_BINOP (cond_and, 64, v64qi, &)
+DEF_COND_BINOP (cond_and, 128, v128qi, &)
+DEF_COND_BINOP (cond_and, 256, v256qi, &)
+DEF_COND_BINOP (cond_and, 512, v512qi, &)
+DEF_COND_BINOP (cond_and, 1024, v1024qi, &)
+DEF_COND_BINOP (cond_and, 2048, v2048qi, &)
+DEF_COND_BINOP (cond_and, 4096, v4096qi, &)
+
+DEF_COND_BINOP (cond_and, 4, v4hi, &)
+DEF_COND_BINOP (cond_and, 8, v8hi, &)
+DEF_COND_BINOP (cond_and, 16, v16hi, &)
+DEF_COND_BINOP (cond_and, 32, v32hi, &)
+DEF_COND_BINOP (cond_and, 64, v64hi, &)
+DEF_COND_BINOP (cond_and, 128, v128hi, &)
+DEF_COND_BINOP (cond_and, 256, v256hi, &)
+DEF_COND_BINOP (cond_and, 512, v512hi, &)
+DEF_COND_BINOP (cond_and, 1024, v1024hi, &)
+DEF_COND_BINOP (cond_and, 2048, v2048hi, &)
+
+DEF_COND_BINOP (cond_and, 4, v4si, &)
+DEF_COND_BINOP (cond_and, 8, v8si, &)
+DEF_COND_BINOP (cond_and, 16, v16si, &)
+DEF_COND_BINOP (cond_and, 32, v32si, &)
+DEF_COND_BINOP (cond_and, 64, v64si, &)
+DEF_COND_BINOP (cond_and, 128, v128si, &)
+DEF_COND_BINOP (cond_and, 256, v256si, &)
+DEF_COND_BINOP (cond_and, 512, v512si, &)
+DEF_COND_BINOP (cond_and, 1024, v1024si, &)
+
+DEF_COND_BINOP (cond_and, 4, v4di, &)
+DEF_COND_BINOP (cond_and, 8, v8di, &)
+DEF_COND_BINOP (cond_and, 16, v16di, &)
+DEF_COND_BINOP (cond_and, 32, v32di, &)
+DEF_COND_BINOP (cond_and, 64, v64di, &)
+DEF_COND_BINOP (cond_and, 128, v128di, &)
+DEF_COND_BINOP (cond_and, 256, v256di, &)
+DEF_COND_BINOP (cond_and, 512, v512di, &)
+
+DEF_COND_BINOP (cond_and, 4, v4uqi, &)
+DEF_COND_BINOP (cond_and, 8, v8uqi, &)
+DEF_COND_BINOP (cond_and, 16, v16uqi, &)
+DEF_COND_BINOP (cond_and, 32, v32uqi, &)
+DEF_COND_BINOP (cond_and, 64, v64uqi, &)
+DEF_COND_BINOP (cond_and, 128, v128uqi, &)
+DEF_COND_BINOP (cond_and, 256, v256uqi, &)
+DEF_COND_BINOP (cond_and, 512, v512uqi, &)
+DEF_COND_BINOP (cond_and, 1024, v1024uqi, &)
+DEF_COND_BINOP (cond_and, 2048, v2048uqi, &)
+DEF_COND_BINOP (cond_and, 4096, v4096uqi, &)
+
+DEF_COND_BINOP (cond_and, 4, v4uhi, &)
+DEF_COND_BINOP (cond_and, 8, v8uhi, &)
+DEF_COND_BINOP (cond_and, 16, v16uhi, &)
+DEF_COND_BINOP (cond_and, 32, v32uhi, &)
+DEF_COND_BINOP (cond_and, 64, v64uhi, &)
+DEF_COND_BINOP (cond_and, 128, v128uhi, &)
+DEF_COND_BINOP (cond_and, 256, v256uhi, &)
+DEF_COND_BINOP (cond_and, 512, v512uhi, &)
+DEF_COND_BINOP (cond_and, 1024, v1024uhi, &)
+DEF_COND_BINOP (cond_and, 2048, v2048uhi, &)
+
+DEF_COND_BINOP (cond_and, 4, v4usi, &)
+DEF_COND_BINOP (cond_and, 8, v8usi, &)
+DEF_COND_BINOP (cond_and, 16, v16usi, &)
+DEF_COND_BINOP (cond_and, 32, v32usi, &)
+DEF_COND_BINOP (cond_and, 64, v64usi, &)
+DEF_COND_BINOP (cond_and, 128, v128usi, &)
+DEF_COND_BINOP (cond_and, 256, v256usi, &)
+DEF_COND_BINOP (cond_and, 512, v512usi, &)
+DEF_COND_BINOP (cond_and, 1024, v1024usi, &)
+
+DEF_COND_BINOP (cond_and, 4, v4udi, &)
+DEF_COND_BINOP (cond_and, 8, v8udi, &)
+DEF_COND_BINOP (cond_and, 16, v16udi, &)
+DEF_COND_BINOP (cond_and, 32, v32udi, &)
+DEF_COND_BINOP (cond_and, 64, v64udi, &)
+DEF_COND_BINOP (cond_and, 128, v128udi, &)
+DEF_COND_BINOP (cond_and, 256, v256udi, &)
+DEF_COND_BINOP (cond_and, 512, v512udi, &)
+
+/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c
new file mode 100644
index 00000000000..373ff00f95b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_div, 4, v4si, /)
+DEF_COND_BINOP (cond_div, 8, v8si, /)
+DEF_COND_BINOP (cond_div, 16, v16si, /)
+DEF_COND_BINOP (cond_div, 32, v32si, /)
+DEF_COND_BINOP (cond_div, 64, v64si, /)
+DEF_COND_BINOP (cond_div, 128, v128si, /)
+DEF_COND_BINOP (cond_div, 256, v256si, /)
+DEF_COND_BINOP (cond_div, 512, v512si, /)
+DEF_COND_BINOP (cond_div, 1024, v1024si, /)
+
+DEF_COND_BINOP (cond_div, 4, v4di, /)
+DEF_COND_BINOP (cond_div, 8, v8di, /)
+DEF_COND_BINOP (cond_div, 16, v16di, /)
+DEF_COND_BINOP (cond_div, 32, v32di, /)
+DEF_COND_BINOP (cond_div, 64, v64di, /)
+DEF_COND_BINOP (cond_div, 128, v128di, /)
+DEF_COND_BINOP (cond_div, 256, v256di, /)
+DEF_COND_BINOP (cond_div, 512, v512di, /)
+
+DEF_COND_BINOP (cond_div, 4, v4usi, /)
+DEF_COND_BINOP (cond_div, 8, v8usi, /)
+DEF_COND_BINOP (cond_div, 16, v16usi, /)
+DEF_COND_BINOP (cond_div, 32, v32usi, /)
+DEF_COND_BINOP (cond_div, 64, v64usi, /)
+DEF_COND_BINOP (cond_div, 128, v128usi, /)
+DEF_COND_BINOP (cond_div, 256, v256usi, /)
+DEF_COND_BINOP (cond_div, 512, v512usi, /)
+DEF_COND_BINOP (cond_div, 1024, v1024usi, /)
+
+DEF_COND_BINOP (cond_div, 4, v4udi, /)
+DEF_COND_BINOP (cond_div, 8, v8udi, /)
+DEF_COND_BINOP (cond_div, 16, v16udi, /)
+DEF_COND_BINOP (cond_div, 32, v32udi, /)
+DEF_COND_BINOP (cond_div, 64, v64udi, /)
+DEF_COND_BINOP (cond_div, 128, v128udi, /)
+DEF_COND_BINOP (cond_div, 256, v256udi, /)
+DEF_COND_BINOP (cond_div, 512, v512udi, /)
+
+/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 34 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c
new file mode 100644
index 00000000000..fac75ef0775
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_div, 4, v4hf, /)
+DEF_COND_BINOP (cond_div, 8, v8hf, /)
+DEF_COND_BINOP (cond_div, 16, v16hf, /)
+DEF_COND_BINOP (cond_div, 32, v32hf, /)
+DEF_COND_BINOP (cond_div, 64, v64hf, /)
+DEF_COND_BINOP (cond_div, 128, v128hf, /)
+DEF_COND_BINOP (cond_div, 256, v256hf, /)
+DEF_COND_BINOP (cond_div, 512, v512hf, /)
+DEF_COND_BINOP (cond_div, 1024, v1024hf, /)
+DEF_COND_BINOP (cond_div, 2048, v2048hf, /)
+
+DEF_COND_BINOP (cond_div, 4, v4sf, /)
+DEF_COND_BINOP (cond_div, 8, v8sf, /)
+DEF_COND_BINOP (cond_div, 16, v16sf, /)
+DEF_COND_BINOP (cond_div, 32, v32sf, /)
+DEF_COND_BINOP (cond_div, 64, v64sf, /)
+DEF_COND_BINOP (cond_div, 128, v128sf, /)
+DEF_COND_BINOP (cond_div, 256, v256sf, /)
+DEF_COND_BINOP (cond_div, 512, v512sf, /)
+DEF_COND_BINOP (cond_div, 1024, v1024sf, /)
+
+DEF_COND_BINOP (cond_div, 4, v4df, /)
+DEF_COND_BINOP (cond_div, 8, v8df, /)
+DEF_COND_BINOP (cond_div, 16, v16df, /)
+DEF_COND_BINOP (cond_div, 32, v32df, /)
+DEF_COND_BINOP (cond_div, 64, v64df, /)
+DEF_COND_BINOP (cond_div, 128, v128df, /)
+DEF_COND_BINOP (cond_div, 256, v256df, /)
+DEF_COND_BINOP (cond_div, 512, v512df, /)
+
+/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c
new file mode 100644
index 00000000000..54d2f0721f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FMA_VV (cond_fma, 4, v4qi)
+DEF_COND_FMA_VV (cond_fma, 8, v8qi)
+DEF_COND_FMA_VV (cond_fma, 16, v16qi)
+DEF_COND_FMA_VV (cond_fma, 32, v32qi)
+DEF_COND_FMA_VV (cond_fma, 64, v64qi)
+DEF_COND_FMA_VV (cond_fma, 128, v128qi)
+DEF_COND_FMA_VV (cond_fma, 256, v256qi)
+DEF_COND_FMA_VV (cond_fma, 512, v512qi)
+DEF_COND_FMA_VV (cond_fma, 1024, v1024qi)
+DEF_COND_FMA_VV (cond_fma, 2048, v2048qi)
+DEF_COND_FMA_VV (cond_fma, 4096, v4096qi)
+
+DEF_COND_FMA_VV (cond_fma, 4, v4hi)
+DEF_COND_FMA_VV (cond_fma, 8, v8hi)
+DEF_COND_FMA_VV (cond_fma, 16, v16hi)
+DEF_COND_FMA_VV (cond_fma, 32, v32hi)
+DEF_COND_FMA_VV (cond_fma, 64, v64hi)
+DEF_COND_FMA_VV (cond_fma, 128, v128hi)
+DEF_COND_FMA_VV (cond_fma, 256, v256hi)
+DEF_COND_FMA_VV (cond_fma, 512, v512hi)
+DEF_COND_FMA_VV (cond_fma, 1024, v1024hi)
+DEF_COND_FMA_VV (cond_fma, 2048, v2048hi)
+
+DEF_COND_FMA_VV (cond_fma, 4, v4si)
+DEF_COND_FMA_VV (cond_fma, 8, v8si)
+DEF_COND_FMA_VV (cond_fma, 16, v16si)
+DEF_COND_FMA_VV (cond_fma, 32, v32si)
+DEF_COND_FMA_VV (cond_fma, 64, v64si)
+DEF_COND_FMA_VV (cond_fma, 128, v128si)
+DEF_COND_FMA_VV (cond_fma, 256, v256si)
+DEF_COND_FMA_VV (cond_fma, 512, v512si)
+DEF_COND_FMA_VV (cond_fma, 1024, v1024si)
+
+DEF_COND_FMA_VV (cond_fma, 4, v4di)
+DEF_COND_FMA_VV (cond_fma, 8, v8di)
+DEF_COND_FMA_VV (cond_fma, 16, v16di)
+DEF_COND_FMA_VV (cond_fma, 32, v32di)
+DEF_COND_FMA_VV (cond_fma, 64, v64di)
+DEF_COND_FMA_VV (cond_fma, 128, v128di)
+DEF_COND_FMA_VV (cond_fma, 256, v256di)
+DEF_COND_FMA_VV (cond_fma, 512, v512di)
+
+/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c
new file mode 100644
index 00000000000..145f81fa5c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FMA_VV (cond_fma, 4, v4hf)
+DEF_COND_FMA_VV (cond_fma, 8, v8hf)
+DEF_COND_FMA_VV (cond_fma, 16, v16hf)
+DEF_COND_FMA_VV (cond_fma, 32, v32hf)
+DEF_COND_FMA_VV (cond_fma, 64, v64hf)
+DEF_COND_FMA_VV (cond_fma, 128, v128hf)
+DEF_COND_FMA_VV (cond_fma, 256, v256hf)
+DEF_COND_FMA_VV (cond_fma, 512, v512hf)
+DEF_COND_FMA_VV (cond_fma, 1024, v1024hf)
+DEF_COND_FMA_VV (cond_fma, 2048, v2048hf)
+
+DEF_COND_FMA_VV (cond_fma, 4, v4sf)
+DEF_COND_FMA_VV (cond_fma, 8, v8sf)
+DEF_COND_FMA_VV (cond_fma, 16, v16sf)
+DEF_COND_FMA_VV (cond_fma, 32, v32sf)
+DEF_COND_FMA_VV (cond_fma, 64, v64sf)
+DEF_COND_FMA_VV (cond_fma, 128, v128sf)
+DEF_COND_FMA_VV (cond_fma, 256, v256sf)
+DEF_COND_FMA_VV (cond_fma, 512, v512sf)
+DEF_COND_FMA_VV (cond_fma, 1024, v1024sf)
+
+DEF_COND_FMA_VV (cond_fma, 4, v4df)
+DEF_COND_FMA_VV (cond_fma, 8, v8df)
+DEF_COND_FMA_VV (cond_fma, 16, v16df)
+DEF_COND_FMA_VV (cond_fma, 32, v32df)
+DEF_COND_FMA_VV (cond_fma, 64, v64df)
+DEF_COND_FMA_VV (cond_fma, 128, v128df)
+DEF_COND_FMA_VV (cond_fma, 256, v256df)
+DEF_COND_FMA_VV (cond_fma, 512, v512df)
+
+/* { dg-final { scan-assembler-times {vfma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c
new file mode 100644
index 00000000000..bfed1dbec02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FMS_VV (cond_fms, 4, v4hf)
+DEF_COND_FMS_VV (cond_fms, 8, v8hf)
+DEF_COND_FMS_VV (cond_fms, 16, v16hf)
+DEF_COND_FMS_VV (cond_fms, 32, v32hf)
+DEF_COND_FMS_VV (cond_fms, 64, v64hf)
+DEF_COND_FMS_VV (cond_fms, 128, v128hf)
+DEF_COND_FMS_VV (cond_fms, 256, v256hf)
+DEF_COND_FMS_VV (cond_fms, 512, v512hf)
+DEF_COND_FMS_VV (cond_fms, 1024, v1024hf)
+DEF_COND_FMS_VV (cond_fms, 2048, v2048hf)
+
+DEF_COND_FMS_VV (cond_fms, 4, v4sf)
+DEF_COND_FMS_VV (cond_fms, 8, v8sf)
+DEF_COND_FMS_VV (cond_fms, 16, v16sf)
+DEF_COND_FMS_VV (cond_fms, 32, v32sf)
+DEF_COND_FMS_VV (cond_fms, 64, v64sf)
+DEF_COND_FMS_VV (cond_fms, 128, v128sf)
+DEF_COND_FMS_VV (cond_fms, 256, v256sf)
+DEF_COND_FMS_VV (cond_fms, 512, v512sf)
+DEF_COND_FMS_VV (cond_fms, 1024, v1024sf)
+
+DEF_COND_FMS_VV (cond_fms, 4, v4df)
+DEF_COND_FMS_VV (cond_fms, 8, v8df)
+DEF_COND_FMS_VV (cond_fms, 16, v16df)
+DEF_COND_FMS_VV (cond_fms, 32, v32df)
+DEF_COND_FMS_VV (cond_fms, 64, v64df)
+DEF_COND_FMS_VV (cond_fms, 128, v128df)
+DEF_COND_FMS_VV (cond_fms, 256, v256df)
+DEF_COND_FMS_VV (cond_fms, 512, v512df)
+
+/* { dg-final { scan-assembler-times {vfms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c
new file mode 100644
index 00000000000..5871c71fdbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FNMA_VV (cond_fnma, 4, v4qi)
+DEF_COND_FNMA_VV (cond_fnma, 8, v8qi)
+DEF_COND_FNMA_VV (cond_fnma, 16, v16qi)
+DEF_COND_FNMA_VV (cond_fnma, 32, v32qi)
+DEF_COND_FNMA_VV (cond_fnma, 64, v64qi)
+DEF_COND_FNMA_VV (cond_fnma, 128, v128qi)
+DEF_COND_FNMA_VV (cond_fnma, 256, v256qi)
+DEF_COND_FNMA_VV (cond_fnma, 512, v512qi)
+DEF_COND_FNMA_VV (cond_fnma, 1024, v1024qi)
+DEF_COND_FNMA_VV (cond_fnma, 2048, v2048qi)
+DEF_COND_FNMA_VV (cond_fnma, 4096, v4096qi)
+
+DEF_COND_FNMA_VV (cond_fnma, 4, v4hi)
+DEF_COND_FNMA_VV (cond_fnma, 8, v8hi)
+DEF_COND_FNMA_VV (cond_fnma, 16, v16hi)
+DEF_COND_FNMA_VV (cond_fnma, 32, v32hi)
+DEF_COND_FNMA_VV (cond_fnma, 64, v64hi)
+DEF_COND_FNMA_VV (cond_fnma, 128, v128hi)
+DEF_COND_FNMA_VV (cond_fnma, 256, v256hi)
+DEF_COND_FNMA_VV (cond_fnma, 512, v512hi)
+DEF_COND_FNMA_VV (cond_fnma, 1024, v1024hi)
+DEF_COND_FNMA_VV (cond_fnma, 2048, v2048hi)
+
+DEF_COND_FNMA_VV (cond_fnma, 4, v4si)
+DEF_COND_FNMA_VV (cond_fnma, 8, v8si)
+DEF_COND_FNMA_VV (cond_fnma, 16, v16si)
+DEF_COND_FNMA_VV (cond_fnma, 32, v32si)
+DEF_COND_FNMA_VV (cond_fnma, 64, v64si)
+DEF_COND_FNMA_VV (cond_fnma, 128, v128si)
+DEF_COND_FNMA_VV (cond_fnma, 256, v256si)
+DEF_COND_FNMA_VV (cond_fnma, 512, v512si)
+DEF_COND_FNMA_VV (cond_fnma, 1024, v1024si)
+
+DEF_COND_FNMA_VV (cond_fnma, 4, v4di)
+DEF_COND_FNMA_VV (cond_fnma, 8, v8di)
+DEF_COND_FNMA_VV (cond_fnma, 16, v16di)
+DEF_COND_FNMA_VV (cond_fnma, 32, v32di)
+DEF_COND_FNMA_VV (cond_fnma, 64, v64di)
+DEF_COND_FNMA_VV (cond_fnma, 128, v128di)
+DEF_COND_FNMA_VV (cond_fnma, 256, v256di)
+DEF_COND_FNMA_VV (cond_fnma, 512, v512di)
+
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c
new file mode 100644
index 00000000000..f91039aa366
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FNMA_VV (cond_fnma, 4, v4hf)
+DEF_COND_FNMA_VV (cond_fnma, 8, v8hf)
+DEF_COND_FNMA_VV (cond_fnma, 16, v16hf)
+DEF_COND_FNMA_VV (cond_fnma, 32, v32hf)
+DEF_COND_FNMA_VV (cond_fnma, 64, v64hf)
+DEF_COND_FNMA_VV (cond_fnma, 128, v128hf)
+DEF_COND_FNMA_VV (cond_fnma, 256, v256hf)
+DEF_COND_FNMA_VV (cond_fnma, 512, v512hf)
+DEF_COND_FNMA_VV (cond_fnma, 1024, v1024hf)
+DEF_COND_FNMA_VV (cond_fnma, 2048, v2048hf)
+
+DEF_COND_FNMA_VV (cond_fnma, 4, v4sf)
+DEF_COND_FNMA_VV (cond_fnma, 8, v8sf)
+DEF_COND_FNMA_VV (cond_fnma, 16, v16sf)
+DEF_COND_FNMA_VV (cond_fnma, 32, v32sf)
+DEF_COND_FNMA_VV (cond_fnma, 64, v64sf)
+DEF_COND_FNMA_VV (cond_fnma, 128, v128sf)
+DEF_COND_FNMA_VV (cond_fnma, 256, v256sf)
+DEF_COND_FNMA_VV (cond_fnma, 512, v512sf)
+DEF_COND_FNMA_VV (cond_fnma, 1024, v1024sf)
+
+DEF_COND_FNMA_VV (cond_fnma, 4, v4df)
+DEF_COND_FNMA_VV (cond_fnma, 8, v8df)
+DEF_COND_FNMA_VV (cond_fnma, 16, v16df)
+DEF_COND_FNMA_VV (cond_fnma, 32, v32df)
+DEF_COND_FNMA_VV (cond_fnma, 64, v64df)
+DEF_COND_FNMA_VV (cond_fnma, 128, v128df)
+DEF_COND_FNMA_VV (cond_fnma, 256, v256df)
+DEF_COND_FNMA_VV (cond_fnma, 512, v512df)
+
+/* { dg-final { scan-assembler-times {vfnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c
new file mode 100644
index 00000000000..59fae9b4788
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FNMS_VV (cond_fnms, 4, v4hf)
+DEF_COND_FNMS_VV (cond_fnms, 8, v8hf)
+DEF_COND_FNMS_VV (cond_fnms, 16, v16hf)
+DEF_COND_FNMS_VV (cond_fnms, 32, v32hf)
+DEF_COND_FNMS_VV (cond_fnms, 64, v64hf)
+DEF_COND_FNMS_VV (cond_fnms, 128, v128hf)
+DEF_COND_FNMS_VV (cond_fnms, 256, v256hf)
+DEF_COND_FNMS_VV (cond_fnms, 512, v512hf)
+DEF_COND_FNMS_VV (cond_fnms, 1024, v1024hf)
+DEF_COND_FNMS_VV (cond_fnms, 2048, v2048hf)
+
+DEF_COND_FNMS_VV (cond_fnms, 4, v4sf)
+DEF_COND_FNMS_VV (cond_fnms, 8, v8sf)
+DEF_COND_FNMS_VV (cond_fnms, 16, v16sf)
+DEF_COND_FNMS_VV (cond_fnms, 32, v32sf)
+DEF_COND_FNMS_VV (cond_fnms, 64, v64sf)
+DEF_COND_FNMS_VV (cond_fnms, 128, v128sf)
+DEF_COND_FNMS_VV (cond_fnms, 256, v256sf)
+DEF_COND_FNMS_VV (cond_fnms, 512, v512sf)
+DEF_COND_FNMS_VV (cond_fnms, 1024, v1024sf)
+
+DEF_COND_FNMS_VV (cond_fnms, 4, v4df)
+DEF_COND_FNMS_VV (cond_fnms, 8, v8df)
+DEF_COND_FNMS_VV (cond_fnms, 16, v16df)
+DEF_COND_FNMS_VV (cond_fnms, 32, v32df)
+DEF_COND_FNMS_VV (cond_fnms, 64, v64df)
+DEF_COND_FNMS_VV (cond_fnms, 128, v128df)
+DEF_COND_FNMS_VV (cond_fnms, 256, v256df)
+DEF_COND_FNMS_VV (cond_fnms, 512, v512df)
+
+/* { dg-final { scan-assembler-times {vfnma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c
new file mode 100644
index 00000000000..2c30854033e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_ior, 4, v4qi, |)
+DEF_COND_BINOP (cond_ior, 8, v8qi, |)
+DEF_COND_BINOP (cond_ior, 16, v16qi, |)
+DEF_COND_BINOP (cond_ior, 32, v32qi, |)
+DEF_COND_BINOP (cond_ior, 64, v64qi, |)
+DEF_COND_BINOP (cond_ior, 128, v128qi, |)
+DEF_COND_BINOP (cond_ior, 256, v256qi, |)
+DEF_COND_BINOP (cond_ior, 512, v512qi, |)
+DEF_COND_BINOP (cond_ior, 1024, v1024qi, |)
+DEF_COND_BINOP (cond_ior, 2048, v2048qi, |)
+DEF_COND_BINOP (cond_ior, 4096, v4096qi, |)
+
+DEF_COND_BINOP (cond_ior, 4, v4hi, |)
+DEF_COND_BINOP (cond_ior, 8, v8hi, |)
+DEF_COND_BINOP (cond_ior, 16, v16hi, |)
+DEF_COND_BINOP (cond_ior, 32, v32hi, |)
+DEF_COND_BINOP (cond_ior, 64, v64hi, |)
+DEF_COND_BINOP (cond_ior, 128, v128hi, |)
+DEF_COND_BINOP (cond_ior, 256, v256hi, |)
+DEF_COND_BINOP (cond_ior, 512, v512hi, |)
+DEF_COND_BINOP (cond_ior, 1024, v1024hi, |)
+DEF_COND_BINOP (cond_ior, 2048, v2048hi, |)
+
+DEF_COND_BINOP (cond_ior, 4, v4si, |)
+DEF_COND_BINOP (cond_ior, 8, v8si, |)
+DEF_COND_BINOP (cond_ior, 16, v16si, |)
+DEF_COND_BINOP (cond_ior, 32, v32si, |)
+DEF_COND_BINOP (cond_ior, 64, v64si, |)
+DEF_COND_BINOP (cond_ior, 128, v128si, |)
+DEF_COND_BINOP (cond_ior, 256, v256si, |)
+DEF_COND_BINOP (cond_ior, 512, v512si, |)
+DEF_COND_BINOP (cond_ior, 1024, v1024si, |)
+
+DEF_COND_BINOP (cond_ior, 4, v4di, |)
+DEF_COND_BINOP (cond_ior, 8, v8di, |)
+DEF_COND_BINOP (cond_ior, 16, v16di, |)
+DEF_COND_BINOP (cond_ior, 32, v32di, |)
+DEF_COND_BINOP (cond_ior, 64, v64di, |)
+DEF_COND_BINOP (cond_ior, 128, v128di, |)
+DEF_COND_BINOP (cond_ior, 256, v256di, |)
+DEF_COND_BINOP (cond_ior, 512, v512di, |)
+
+DEF_COND_BINOP (cond_ior, 4, v4uqi, |)
+DEF_COND_BINOP (cond_ior, 8, v8uqi, |)
+DEF_COND_BINOP (cond_ior, 16, v16uqi, |)
+DEF_COND_BINOP (cond_ior, 32, v32uqi, |)
+DEF_COND_BINOP (cond_ior, 64, v64uqi, |)
+DEF_COND_BINOP (cond_ior, 128, v128uqi, |)
+DEF_COND_BINOP (cond_ior, 256, v256uqi, |)
+DEF_COND_BINOP (cond_ior, 512, v512uqi, |)
+DEF_COND_BINOP (cond_ior, 1024, v1024uqi, |)
+DEF_COND_BINOP (cond_ior, 2048, v2048uqi, |)
+DEF_COND_BINOP (cond_ior, 4096, v4096uqi, |)
+
+DEF_COND_BINOP (cond_ior, 4, v4uhi, |)
+DEF_COND_BINOP (cond_ior, 8, v8uhi, |)
+DEF_COND_BINOP (cond_ior, 16, v16uhi, |)
+DEF_COND_BINOP (cond_ior, 32, v32uhi, |)
+DEF_COND_BINOP (cond_ior, 64, v64uhi, |)
+DEF_COND_BINOP (cond_ior, 128, v128uhi, |)
+DEF_COND_BINOP (cond_ior, 256, v256uhi, |)
+DEF_COND_BINOP (cond_ior, 512, v512uhi, |)
+DEF_COND_BINOP (cond_ior, 1024, v1024uhi, |)
+DEF_COND_BINOP (cond_ior, 2048, v2048uhi, |)
+
+DEF_COND_BINOP (cond_ior, 4, v4usi, |)
+DEF_COND_BINOP (cond_ior, 8, v8usi, |)
+DEF_COND_BINOP (cond_ior, 16, v16usi, |)
+DEF_COND_BINOP (cond_ior, 32, v32usi, |)
+DEF_COND_BINOP (cond_ior, 64, v64usi, |)
+DEF_COND_BINOP (cond_ior, 128, v128usi, |)
+DEF_COND_BINOP (cond_ior, 256, v256usi, |)
+DEF_COND_BINOP (cond_ior, 512, v512usi, |)
+DEF_COND_BINOP (cond_ior, 1024, v1024usi, |)
+
+DEF_COND_BINOP (cond_ior, 4, v4udi, |)
+DEF_COND_BINOP (cond_ior, 8, v8udi, |)
+DEF_COND_BINOP (cond_ior, 16, v16udi, |)
+DEF_COND_BINOP (cond_ior, 32, v32udi, |)
+DEF_COND_BINOP (cond_ior, 64, v64udi, |)
+DEF_COND_BINOP (cond_ior, 128, v128udi, |)
+DEF_COND_BINOP (cond_ior, 256, v256udi, |)
+DEF_COND_BINOP (cond_ior, 512, v512udi, |)
+
+/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c
new file mode 100644
index 00000000000..60e0f9391d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_MINMAX (cond_max, 4, v4qi, >=)
+DEF_COND_MINMAX (cond_max, 8, v8qi, >=)
+DEF_COND_MINMAX (cond_max, 16, v16qi, >=)
+DEF_COND_MINMAX (cond_max, 32, v32qi, >=)
+DEF_COND_MINMAX (cond_max, 64, v64qi, >=)
+DEF_COND_MINMAX (cond_max, 128, v128qi, >=)
+DEF_COND_MINMAX (cond_max, 256, v256qi, >=)
+DEF_COND_MINMAX (cond_max, 512, v512qi, >=)
+DEF_COND_MINMAX (cond_max, 1024, v1024qi, >=)
+DEF_COND_MINMAX (cond_max, 2048, v2048qi, >=)
+DEF_COND_MINMAX (cond_max, 4096, v4096qi, >=)
+
+DEF_COND_MINMAX (cond_max, 4, v4hi, >=)
+DEF_COND_MINMAX (cond_max, 8, v8hi, >=)
+DEF_COND_MINMAX (cond_max, 16, v16hi, >=)
+DEF_COND_MINMAX (cond_max, 32, v32hi, >=)
+DEF_COND_MINMAX (cond_max, 64, v64hi, >=)
+DEF_COND_MINMAX (cond_max, 128, v128hi, >=)
+DEF_COND_MINMAX (cond_max, 256, v256hi, >=)
+DEF_COND_MINMAX (cond_max, 512, v512hi, >=)
+DEF_COND_MINMAX (cond_max, 1024, v1024hi, >=)
+DEF_COND_MINMAX (cond_max, 2048, v2048hi, >=)
+
+DEF_COND_MINMAX (cond_max, 4, v4si, >=)
+DEF_COND_MINMAX (cond_max, 8, v8si, >=)
+DEF_COND_MINMAX (cond_max, 16, v16si, >=)
+DEF_COND_MINMAX (cond_max, 32, v32si, >=)
+DEF_COND_MINMAX (cond_max, 64, v64si, >=)
+DEF_COND_MINMAX (cond_max, 128, v128si, >=)
+DEF_COND_MINMAX (cond_max, 256, v256si, >=)
+DEF_COND_MINMAX (cond_max, 512, v512si, >=)
+DEF_COND_MINMAX (cond_max, 1024, v1024si, >=)
+
+DEF_COND_MINMAX (cond_max, 4, v4di, >=)
+DEF_COND_MINMAX (cond_max, 8, v8di, >=)
+DEF_COND_MINMAX (cond_max, 16, v16di, >=)
+DEF_COND_MINMAX (cond_max, 32, v32di, >=)
+DEF_COND_MINMAX (cond_max, 64, v64di, >=)
+DEF_COND_MINMAX (cond_max, 128, v128di, >=)
+DEF_COND_MINMAX (cond_max, 256, v256di, >=)
+DEF_COND_MINMAX (cond_max, 512, v512di, >=)
+
+DEF_COND_MINMAX (cond_max, 4, v4uqi, >=)
+DEF_COND_MINMAX (cond_max, 8, v8uqi, >=)
+DEF_COND_MINMAX (cond_max, 16, v16uqi, >=)
+DEF_COND_MINMAX (cond_max, 32, v32uqi, >=)
+DEF_COND_MINMAX (cond_max, 64, v64uqi, >=)
+DEF_COND_MINMAX (cond_max, 128, v128uqi, >=)
+DEF_COND_MINMAX (cond_max, 256, v256uqi, >=)
+DEF_COND_MINMAX (cond_max, 512, v512uqi, >=)
+DEF_COND_MINMAX (cond_max, 1024, v1024uqi, >=)
+DEF_COND_MINMAX (cond_max, 2048, v2048uqi, >=)
+DEF_COND_MINMAX (cond_max, 4096, v4096uqi, >=)
+
+DEF_COND_MINMAX (cond_max, 4, v4uhi, >=)
+DEF_COND_MINMAX (cond_max, 8, v8uhi, >=)
+DEF_COND_MINMAX (cond_max, 16, v16uhi, >=)
+DEF_COND_MINMAX (cond_max, 32, v32uhi, >=)
+DEF_COND_MINMAX (cond_max, 64, v64uhi, >=)
+DEF_COND_MINMAX (cond_max, 128, v128uhi, >=)
+DEF_COND_MINMAX (cond_max, 256, v256uhi, >=)
+DEF_COND_MINMAX (cond_max, 512, v512uhi, >=)
+DEF_COND_MINMAX (cond_max, 1024, v1024uhi, >=)
+DEF_COND_MINMAX (cond_max, 2048, v2048uhi, >=)
+
+DEF_COND_MINMAX (cond_max, 4, v4usi, >=)
+DEF_COND_MINMAX (cond_max, 8, v8usi, >=)
+DEF_COND_MINMAX (cond_max, 16, v16usi, >=)
+DEF_COND_MINMAX (cond_max, 32, v32usi, >=)
+DEF_COND_MINMAX (cond_max, 64, v64usi, >=)
+DEF_COND_MINMAX (cond_max, 128, v128usi, >=)
+DEF_COND_MINMAX (cond_max, 256, v256usi, >=)
+DEF_COND_MINMAX (cond_max, 512, v512usi, >=)
+DEF_COND_MINMAX (cond_max, 1024, v1024usi, >=)
+
+DEF_COND_MINMAX (cond_max, 4, v4udi, >=)
+DEF_COND_MINMAX (cond_max, 8, v8udi, >=)
+DEF_COND_MINMAX (cond_max, 16, v16udi, >=)
+DEF_COND_MINMAX (cond_max, 32, v32udi, >=)
+DEF_COND_MINMAX (cond_max, 64, v64udi, >=)
+DEF_COND_MINMAX (cond_max, 128, v128udi, >=)
+DEF_COND_MINMAX (cond_max, 256, v256udi, >=)
+DEF_COND_MINMAX (cond_max, 512, v512udi, >=)
+
+/* { dg-final { scan-assembler-times {vmaxu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c
new file mode 100644
index 00000000000..f8db2925b52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_MINMAX (cond_max, 4, v4hf, >=)
+DEF_COND_MINMAX (cond_max, 8, v8hf, >=)
+DEF_COND_MINMAX (cond_max, 16, v16hf, >=)
+DEF_COND_MINMAX (cond_max, 32, v32hf, >=)
+DEF_COND_MINMAX (cond_max, 64, v64hf, >=)
+DEF_COND_MINMAX (cond_max, 128, v128hf, >=)
+DEF_COND_MINMAX (cond_max, 256, v256hf, >=)
+DEF_COND_MINMAX (cond_max, 512, v512hf, >=)
+DEF_COND_MINMAX (cond_max, 1024, v1024hf, >=)
+DEF_COND_MINMAX (cond_max, 2048, v2048hf, >=)
+
+DEF_COND_MINMAX (cond_max, 4, v4sf, >=)
+DEF_COND_MINMAX (cond_max, 8, v8sf, >=)
+DEF_COND_MINMAX (cond_max, 16, v16sf, >=)
+DEF_COND_MINMAX (cond_max, 32, v32sf, >=)
+DEF_COND_MINMAX (cond_max, 64, v64sf, >=)
+DEF_COND_MINMAX (cond_max, 128, v128sf, >=)
+DEF_COND_MINMAX (cond_max, 256, v256sf, >=)
+DEF_COND_MINMAX (cond_max, 512, v512sf, >=)
+DEF_COND_MINMAX (cond_max, 1024, v1024sf, >=)
+
+DEF_COND_MINMAX (cond_max, 4, v4df, >=)
+DEF_COND_MINMAX (cond_max, 8, v8df, >=)
+DEF_COND_MINMAX (cond_max, 16, v16df, >=)
+DEF_COND_MINMAX (cond_max, 32, v32df, >=)
+DEF_COND_MINMAX (cond_max, 64, v64df, >=)
+DEF_COND_MINMAX (cond_max, 128, v128df, >=)
+DEF_COND_MINMAX (cond_max, 256, v256df, >=)
+DEF_COND_MINMAX (cond_max, 512, v512df, >=)
+
+/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c
new file mode 100644
index 00000000000..2a13c254e7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_MINMAX (cond_min, 4, v4qi, <=)
+DEF_COND_MINMAX (cond_min, 8, v8qi, <=)
+DEF_COND_MINMAX (cond_min, 16, v16qi, <=)
+DEF_COND_MINMAX (cond_min, 32, v32qi, <=)
+DEF_COND_MINMAX (cond_min, 64, v64qi, <=)
+DEF_COND_MINMAX (cond_min, 128, v128qi, <=)
+DEF_COND_MINMAX (cond_min, 256, v256qi, <=)
+DEF_COND_MINMAX (cond_min, 512, v512qi, <=)
+DEF_COND_MINMAX (cond_min, 1024, v1024qi, <=)
+DEF_COND_MINMAX (cond_min, 2048, v2048qi, <=)
+DEF_COND_MINMAX (cond_min, 4096, v4096qi, <=)
+
+DEF_COND_MINMAX (cond_min, 4, v4hi, <=)
+DEF_COND_MINMAX (cond_min, 8, v8hi, <=)
+DEF_COND_MINMAX (cond_min, 16, v16hi, <=)
+DEF_COND_MINMAX (cond_min, 32, v32hi, <=)
+DEF_COND_MINMAX (cond_min, 64, v64hi, <=)
+DEF_COND_MINMAX (cond_min, 128, v128hi, <=)
+DEF_COND_MINMAX (cond_min, 256, v256hi, <=)
+DEF_COND_MINMAX (cond_min, 512, v512hi, <=)
+DEF_COND_MINMAX (cond_min, 1024, v1024hi, <=)
+DEF_COND_MINMAX (cond_min, 2048, v2048hi, <=)
+
+DEF_COND_MINMAX (cond_min, 4, v4si, <=)
+DEF_COND_MINMAX (cond_min, 8, v8si, <=)
+DEF_COND_MINMAX (cond_min, 16, v16si, <=)
+DEF_COND_MINMAX (cond_min, 32, v32si, <=)
+DEF_COND_MINMAX (cond_min, 64, v64si, <=)
+DEF_COND_MINMAX (cond_min, 128, v128si, <=)
+DEF_COND_MINMAX (cond_min, 256, v256si, <=)
+DEF_COND_MINMAX (cond_min, 512, v512si, <=)
+DEF_COND_MINMAX (cond_min, 1024, v1024si, <=)
+
+DEF_COND_MINMAX (cond_min, 4, v4di, <=)
+DEF_COND_MINMAX (cond_min, 8, v8di, <=)
+DEF_COND_MINMAX (cond_min, 16, v16di, <=)
+DEF_COND_MINMAX (cond_min, 32, v32di, <=)
+DEF_COND_MINMAX (cond_min, 64, v64di, <=)
+DEF_COND_MINMAX (cond_min, 128, v128di, <=)
+DEF_COND_MINMAX (cond_min, 256, v256di, <=)
+DEF_COND_MINMAX (cond_min, 512, v512di, <=)
+
+DEF_COND_MINMAX (cond_min, 4, v4uqi, <=)
+DEF_COND_MINMAX (cond_min, 8, v8uqi, <=)
+DEF_COND_MINMAX (cond_min, 16, v16uqi, <=)
+DEF_COND_MINMAX (cond_min, 32, v32uqi, <=)
+DEF_COND_MINMAX (cond_min, 64, v64uqi, <=)
+DEF_COND_MINMAX (cond_min, 128, v128uqi, <=)
+DEF_COND_MINMAX (cond_min, 256, v256uqi, <=)
+DEF_COND_MINMAX (cond_min, 512, v512uqi, <=)
+DEF_COND_MINMAX (cond_min, 1024, v1024uqi, <=)
+DEF_COND_MINMAX (cond_min, 2048, v2048uqi, <=)
+DEF_COND_MINMAX (cond_min, 4096, v4096uqi, <=)
+
+DEF_COND_MINMAX (cond_min, 4, v4uhi, <=)
+DEF_COND_MINMAX (cond_min, 8, v8uhi, <=)
+DEF_COND_MINMAX (cond_min, 16, v16uhi, <=)
+DEF_COND_MINMAX (cond_min, 32, v32uhi, <=)
+DEF_COND_MINMAX (cond_min, 64, v64uhi, <=)
+DEF_COND_MINMAX (cond_min, 128, v128uhi, <=)
+DEF_COND_MINMAX (cond_min, 256, v256uhi, <=)
+DEF_COND_MINMAX (cond_min, 512, v512uhi, <=)
+DEF_COND_MINMAX (cond_min, 1024, v1024uhi, <=)
+DEF_COND_MINMAX (cond_min, 2048, v2048uhi, <=)
+
+DEF_COND_MINMAX (cond_min, 4, v4usi, <=)
+DEF_COND_MINMAX (cond_min, 8, v8usi, <=)
+DEF_COND_MINMAX (cond_min, 16, v16usi, <=)
+DEF_COND_MINMAX (cond_min, 32, v32usi, <=)
+DEF_COND_MINMAX (cond_min, 64, v64usi, <=)
+DEF_COND_MINMAX (cond_min, 128, v128usi, <=)
+DEF_COND_MINMAX (cond_min, 256, v256usi, <=)
+DEF_COND_MINMAX (cond_min, 512, v512usi, <=)
+DEF_COND_MINMAX (cond_min, 1024, v1024usi, <=)
+
+DEF_COND_MINMAX (cond_min, 4, v4udi, <=)
+DEF_COND_MINMAX (cond_min, 8, v8udi, <=)
+DEF_COND_MINMAX (cond_min, 16, v16udi, <=)
+DEF_COND_MINMAX (cond_min, 32, v32udi, <=)
+DEF_COND_MINMAX (cond_min, 64, v64udi, <=)
+DEF_COND_MINMAX (cond_min, 128, v128udi, <=)
+DEF_COND_MINMAX (cond_min, 256, v256udi, <=)
+DEF_COND_MINMAX (cond_min, 512, v512udi, <=)
+
+/* { dg-final { scan-assembler-times {vminu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c
new file mode 100644
index 00000000000..0ae82085b1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_MINMAX (cond_min, 4, v4hf, <=)
+DEF_COND_MINMAX (cond_min, 8, v8hf, <=)
+DEF_COND_MINMAX (cond_min, 16, v16hf, <=)
+DEF_COND_MINMAX (cond_min, 32, v32hf, <=)
+DEF_COND_MINMAX (cond_min, 64, v64hf, <=)
+DEF_COND_MINMAX (cond_min, 128, v128hf, <=)
+DEF_COND_MINMAX (cond_min, 256, v256hf, <=)
+DEF_COND_MINMAX (cond_min, 512, v512hf, <=)
+DEF_COND_MINMAX (cond_min, 1024, v1024hf, <=)
+DEF_COND_MINMAX (cond_min, 2048, v2048hf, <=)
+
+DEF_COND_MINMAX (cond_min, 4, v4sf, <=)
+DEF_COND_MINMAX (cond_min, 8, v8sf, <=)
+DEF_COND_MINMAX (cond_min, 16, v16sf, <=)
+DEF_COND_MINMAX (cond_min, 32, v32sf, <=)
+DEF_COND_MINMAX (cond_min, 64, v64sf, <=)
+DEF_COND_MINMAX (cond_min, 128, v128sf, <=)
+DEF_COND_MINMAX (cond_min, 256, v256sf, <=)
+DEF_COND_MINMAX (cond_min, 512, v512sf, <=)
+DEF_COND_MINMAX (cond_min, 1024, v1024sf, <=)
+
+DEF_COND_MINMAX (cond_min, 4, v4df, <=)
+DEF_COND_MINMAX (cond_min, 8, v8df, <=)
+DEF_COND_MINMAX (cond_min, 16, v16df, <=)
+DEF_COND_MINMAX (cond_min, 32, v32df, <=)
+DEF_COND_MINMAX (cond_min, 64, v64df, <=)
+DEF_COND_MINMAX (cond_min, 128, v128df, <=)
+DEF_COND_MINMAX (cond_min, 256, v256df, <=)
+DEF_COND_MINMAX (cond_min, 512, v512df, <=)
+
+/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c
new file mode 100644
index 00000000000..060c58bfe5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_rem, 4, v4si, %)
+DEF_COND_BINOP (cond_rem, 8, v8si, %)
+DEF_COND_BINOP (cond_rem, 16, v16si, %)
+DEF_COND_BINOP (cond_rem, 32, v32si, %)
+DEF_COND_BINOP (cond_rem, 64, v64si, %)
+DEF_COND_BINOP (cond_rem, 128, v128si, %)
+DEF_COND_BINOP (cond_rem, 256, v256si, %)
+DEF_COND_BINOP (cond_rem, 512, v512si, %)
+DEF_COND_BINOP (cond_rem, 1024, v1024si, %)
+
+DEF_COND_BINOP (cond_rem, 4, v4di, %)
+DEF_COND_BINOP (cond_rem, 8, v8di, %)
+DEF_COND_BINOP (cond_rem, 16, v16di, %)
+DEF_COND_BINOP (cond_rem, 32, v32di, %)
+DEF_COND_BINOP (cond_rem, 64, v64di, %)
+DEF_COND_BINOP (cond_rem, 128, v128di, %)
+DEF_COND_BINOP (cond_rem, 256, v256di, %)
+DEF_COND_BINOP (cond_rem, 512, v512di, %)
+
+DEF_COND_BINOP (cond_rem, 4, v4usi, %)
+DEF_COND_BINOP (cond_rem, 8, v8usi, %)
+DEF_COND_BINOP (cond_rem, 16, v16usi, %)
+DEF_COND_BINOP (cond_rem, 32, v32usi, %)
+DEF_COND_BINOP (cond_rem, 64, v64usi, %)
+DEF_COND_BINOP (cond_rem, 128, v128usi, %)
+DEF_COND_BINOP (cond_rem, 256, v256usi, %)
+DEF_COND_BINOP (cond_rem, 512, v512usi, %)
+DEF_COND_BINOP (cond_rem, 1024, v1024usi, %)
+
+DEF_COND_BINOP (cond_rem, 4, v4udi, %)
+DEF_COND_BINOP (cond_rem, 8, v8udi, %)
+DEF_COND_BINOP (cond_rem, 16, v16udi, %)
+DEF_COND_BINOP (cond_rem, 32, v32udi, %)
+DEF_COND_BINOP (cond_rem, 64, v64udi, %)
+DEF_COND_BINOP (cond_rem, 128, v128udi, %)
+DEF_COND_BINOP (cond_rem, 256, v256udi, %)
+DEF_COND_BINOP (cond_rem, 512, v512udi, %)
+
+/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 34 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c
new file mode 100644
index 00000000000..f6b58c101ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_mul, 4, v4qi, *)
+DEF_COND_BINOP (cond_mul, 8, v8qi, *)
+DEF_COND_BINOP (cond_mul, 16, v16qi, *)
+DEF_COND_BINOP (cond_mul, 32, v32qi, *)
+DEF_COND_BINOP (cond_mul, 64, v64qi, *)
+DEF_COND_BINOP (cond_mul, 128, v128qi, *)
+DEF_COND_BINOP (cond_mul, 256, v256qi, *)
+DEF_COND_BINOP (cond_mul, 512, v512qi, *)
+DEF_COND_BINOP (cond_mul, 1024, v1024qi, *)
+DEF_COND_BINOP (cond_mul, 2048, v2048qi, *)
+DEF_COND_BINOP (cond_mul, 4096, v4096qi, *)
+
+DEF_COND_BINOP (cond_mul, 4, v4hi, *)
+DEF_COND_BINOP (cond_mul, 8, v8hi, *)
+DEF_COND_BINOP (cond_mul, 16, v16hi, *)
+DEF_COND_BINOP (cond_mul, 32, v32hi, *)
+DEF_COND_BINOP (cond_mul, 64, v64hi, *)
+DEF_COND_BINOP (cond_mul, 128, v128hi, *)
+DEF_COND_BINOP (cond_mul, 256, v256hi, *)
+DEF_COND_BINOP (cond_mul, 512, v512hi, *)
+DEF_COND_BINOP (cond_mul, 1024, v1024hi, *)
+DEF_COND_BINOP (cond_mul, 2048, v2048hi, *)
+
+DEF_COND_BINOP (cond_mul, 4, v4si, *)
+DEF_COND_BINOP (cond_mul, 8, v8si, *)
+DEF_COND_BINOP (cond_mul, 16, v16si, *)
+DEF_COND_BINOP (cond_mul, 32, v32si, *)
+DEF_COND_BINOP (cond_mul, 64, v64si, *)
+DEF_COND_BINOP (cond_mul, 128, v128si, *)
+DEF_COND_BINOP (cond_mul, 256, v256si, *)
+DEF_COND_BINOP (cond_mul, 512, v512si, *)
+DEF_COND_BINOP (cond_mul, 1024, v1024si, *)
+
+DEF_COND_BINOP (cond_mul, 4, v4di, *)
+DEF_COND_BINOP (cond_mul, 8, v8di, *)
+DEF_COND_BINOP (cond_mul, 16, v16di, *)
+DEF_COND_BINOP (cond_mul, 32, v32di, *)
+DEF_COND_BINOP (cond_mul, 64, v64di, *)
+DEF_COND_BINOP (cond_mul, 128, v128di, *)
+DEF_COND_BINOP (cond_mul, 256, v256di, *)
+DEF_COND_BINOP (cond_mul, 512, v512di, *)
+
+DEF_COND_BINOP (cond_mul, 4, v4uqi, *)
+DEF_COND_BINOP (cond_mul, 8, v8uqi, *)
+DEF_COND_BINOP (cond_mul, 16, v16uqi, *)
+DEF_COND_BINOP (cond_mul, 32, v32uqi, *)
+DEF_COND_BINOP (cond_mul, 64, v64uqi, *)
+DEF_COND_BINOP (cond_mul, 128, v128uqi, *)
+DEF_COND_BINOP (cond_mul, 256, v256uqi, *)
+DEF_COND_BINOP (cond_mul, 512, v512uqi, *)
+DEF_COND_BINOP (cond_mul, 1024, v1024uqi, *)
+DEF_COND_BINOP (cond_mul, 2048, v2048uqi, *)
+DEF_COND_BINOP (cond_mul, 4096, v4096uqi, *)
+
+DEF_COND_BINOP (cond_mul, 4, v4uhi, *)
+DEF_COND_BINOP (cond_mul, 8, v8uhi, *)
+DEF_COND_BINOP (cond_mul, 16, v16uhi, *)
+DEF_COND_BINOP (cond_mul, 32, v32uhi, *)
+DEF_COND_BINOP (cond_mul, 64, v64uhi, *)
+DEF_COND_BINOP (cond_mul, 128, v128uhi, *)
+DEF_COND_BINOP (cond_mul, 256, v256uhi, *)
+DEF_COND_BINOP (cond_mul, 512, v512uhi, *)
+DEF_COND_BINOP (cond_mul, 1024, v1024uhi, *)
+DEF_COND_BINOP (cond_mul, 2048, v2048uhi, *)
+
+DEF_COND_BINOP (cond_mul, 4, v4usi, *)
+DEF_COND_BINOP (cond_mul, 8, v8usi, *)
+DEF_COND_BINOP (cond_mul, 16, v16usi, *)
+DEF_COND_BINOP (cond_mul, 32, v32usi, *)
+DEF_COND_BINOP (cond_mul, 64, v64usi, *)
+DEF_COND_BINOP (cond_mul, 128, v128usi, *)
+DEF_COND_BINOP (cond_mul, 256, v256usi, *)
+DEF_COND_BINOP (cond_mul, 512, v512usi, *)
+DEF_COND_BINOP (cond_mul, 1024, v1024usi, *)
+
+DEF_COND_BINOP (cond_mul, 4, v4udi, *)
+DEF_COND_BINOP (cond_mul, 8, v8udi, *)
+DEF_COND_BINOP (cond_mul, 16, v16udi, *)
+DEF_COND_BINOP (cond_mul, 32, v32udi, *)
+DEF_COND_BINOP (cond_mul, 64, v64udi, *)
+DEF_COND_BINOP (cond_mul, 128, v128udi, *)
+DEF_COND_BINOP (cond_mul, 256, v256udi, *)
+DEF_COND_BINOP (cond_mul, 512, v512udi, *)
+
+/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c
new file mode 100644
index 00000000000..4df3d5579b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_mul, 4, v4hf, *)
+DEF_COND_BINOP (cond_mul, 8, v8hf, *)
+DEF_COND_BINOP (cond_mul, 16, v16hf, *)
+DEF_COND_BINOP (cond_mul, 32, v32hf, *)
+DEF_COND_BINOP (cond_mul, 64, v64hf, *)
+DEF_COND_BINOP (cond_mul, 128, v128hf, *)
+DEF_COND_BINOP (cond_mul, 256, v256hf, *)
+DEF_COND_BINOP (cond_mul, 512, v512hf, *)
+DEF_COND_BINOP (cond_mul, 1024, v1024hf, *)
+DEF_COND_BINOP (cond_mul, 2048, v2048hf, *)
+
+DEF_COND_BINOP (cond_mul, 4, v4sf, *)
+DEF_COND_BINOP (cond_mul, 8, v8sf, *)
+DEF_COND_BINOP (cond_mul, 16, v16sf, *)
+DEF_COND_BINOP (cond_mul, 32, v32sf, *)
+DEF_COND_BINOP (cond_mul, 64, v64sf, *)
+DEF_COND_BINOP (cond_mul, 128, v128sf, *)
+DEF_COND_BINOP (cond_mul, 256, v256sf, *)
+DEF_COND_BINOP (cond_mul, 512, v512sf, *)
+DEF_COND_BINOP (cond_mul, 1024, v1024sf, *)
+
+DEF_COND_BINOP (cond_mul, 4, v4df, *)
+DEF_COND_BINOP (cond_mul, 8, v8df, *)
+DEF_COND_BINOP (cond_mul, 16, v16df, *)
+DEF_COND_BINOP (cond_mul, 32, v32df, *)
+DEF_COND_BINOP (cond_mul, 64, v64df, *)
+DEF_COND_BINOP (cond_mul, 128, v128df, *)
+DEF_COND_BINOP (cond_mul, 256, v256df, *)
+DEF_COND_BINOP (cond_mul, 512, v512df, *)
+
+/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
new file mode 100644
index 00000000000..ca944460ca7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_UNOP (cond_neg, 4, v4qi, -)
+DEF_COND_UNOP (cond_neg, 8, v8qi, -)
+DEF_COND_UNOP (cond_neg, 16, v16qi, -)
+DEF_COND_UNOP (cond_neg, 32, v32qi, -)
+DEF_COND_UNOP (cond_neg, 64, v64qi, -)
+DEF_COND_UNOP (cond_neg, 128, v128qi, -)
+DEF_COND_UNOP (cond_neg, 256, v256qi, -)
+DEF_COND_UNOP (cond_neg, 512, v512qi, -)
+DEF_COND_UNOP (cond_neg, 1024, v1024qi, -)
+DEF_COND_UNOP (cond_neg, 2048, v2048qi, -)
+DEF_COND_UNOP (cond_neg, 4096, v4096qi, -)
+
+DEF_COND_UNOP (cond_neg, 4, v4hi, -)
+DEF_COND_UNOP (cond_neg, 8, v8hi, -)
+DEF_COND_UNOP (cond_neg, 16, v16hi, -)
+DEF_COND_UNOP (cond_neg, 32, v32hi, -)
+DEF_COND_UNOP (cond_neg, 64, v64hi, -)
+DEF_COND_UNOP (cond_neg, 128, v128hi, -)
+DEF_COND_UNOP (cond_neg, 256, v256hi, -)
+DEF_COND_UNOP (cond_neg, 512, v512hi, -)
+DEF_COND_UNOP (cond_neg, 1024, v1024hi, -)
+DEF_COND_UNOP (cond_neg, 2048, v2048hi, -)
+
+DEF_COND_UNOP (cond_neg, 4, v4si, -)
+DEF_COND_UNOP (cond_neg, 8, v8si, -)
+DEF_COND_UNOP (cond_neg, 16, v16si, -)
+DEF_COND_UNOP (cond_neg, 32, v32si, -)
+DEF_COND_UNOP (cond_neg, 64, v64si, -)
+DEF_COND_UNOP (cond_neg, 128, v128si, -)
+DEF_COND_UNOP (cond_neg, 256, v256si, -)
+DEF_COND_UNOP (cond_neg, 512, v512si, -)
+DEF_COND_UNOP (cond_neg, 1024, v1024si, -)
+
+DEF_COND_UNOP (cond_neg, 4, v4di, -)
+DEF_COND_UNOP (cond_neg, 8, v8di, -)
+DEF_COND_UNOP (cond_neg, 16, v16di, -)
+DEF_COND_UNOP (cond_neg, 32, v32di, -)
+DEF_COND_UNOP (cond_neg, 64, v64di, -)
+DEF_COND_UNOP (cond_neg, 128, v128di, -)
+DEF_COND_UNOP (cond_neg, 256, v256di, -)
+DEF_COND_UNOP (cond_neg, 512, v512di, -)
+
+/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c
new file mode 100644
index 00000000000..cf44c1805e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_UNOP (cond_neg, 4, v4hf, -)
+DEF_COND_UNOP (cond_neg, 8, v8hf, -)
+DEF_COND_UNOP (cond_neg, 16, v16hf, -)
+DEF_COND_UNOP (cond_neg, 32, v32hf, -)
+DEF_COND_UNOP (cond_neg, 64, v64hf, -)
+DEF_COND_UNOP (cond_neg, 128, v128hf, -)
+DEF_COND_UNOP (cond_neg, 256, v256hf, -)
+DEF_COND_UNOP (cond_neg, 512, v512hf, -)
+DEF_COND_UNOP (cond_neg, 1024, v1024hf, -)
+DEF_COND_UNOP (cond_neg, 2048, v2048hf, -)
+
+DEF_COND_UNOP (cond_neg, 4, v4sf, -)
+DEF_COND_UNOP (cond_neg, 8, v8sf, -)
+DEF_COND_UNOP (cond_neg, 16, v16sf, -)
+DEF_COND_UNOP (cond_neg, 32, v32sf, -)
+DEF_COND_UNOP (cond_neg, 64, v64sf, -)
+DEF_COND_UNOP (cond_neg, 128, v128sf, -)
+DEF_COND_UNOP (cond_neg, 256, v256sf, -)
+DEF_COND_UNOP (cond_neg, 512, v512sf, -)
+DEF_COND_UNOP (cond_neg, 1024, v1024sf, -)
+
+DEF_COND_UNOP (cond_neg, 4, v4df, -)
+DEF_COND_UNOP (cond_neg, 8, v8df, -)
+DEF_COND_UNOP (cond_neg, 16, v16df, -)
+DEF_COND_UNOP (cond_neg, 32, v32df, -)
+DEF_COND_UNOP (cond_neg, 64, v64df, -)
+DEF_COND_UNOP (cond_neg, 128, v128df, -)
+DEF_COND_UNOP (cond_neg, 256, v256df, -)
+DEF_COND_UNOP (cond_neg, 512, v512df, -)
+
+/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c
new file mode 100644
index 00000000000..1a2a8f45108
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_UNOP (cond_not, 4, v4qi, ~)
+DEF_COND_UNOP (cond_not, 8, v8qi, ~)
+DEF_COND_UNOP (cond_not, 16, v16qi, ~)
+DEF_COND_UNOP (cond_not, 32, v32qi, ~)
+DEF_COND_UNOP (cond_not, 64, v64qi, ~)
+DEF_COND_UNOP (cond_not, 128, v128qi, ~)
+DEF_COND_UNOP (cond_not, 256, v256qi, ~)
+DEF_COND_UNOP (cond_not, 512, v512qi, ~)
+DEF_COND_UNOP (cond_not, 1024, v1024qi, ~)
+DEF_COND_UNOP (cond_not, 2048, v2048qi, ~)
+DEF_COND_UNOP (cond_not, 4096, v4096qi, ~)
+
+DEF_COND_UNOP (cond_not, 4, v4hi, ~)
+DEF_COND_UNOP (cond_not, 8, v8hi, ~)
+DEF_COND_UNOP (cond_not, 16, v16hi, ~)
+DEF_COND_UNOP (cond_not, 32, v32hi, ~)
+DEF_COND_UNOP (cond_not, 64, v64hi, ~)
+DEF_COND_UNOP (cond_not, 128, v128hi, ~)
+DEF_COND_UNOP (cond_not, 256, v256hi, ~)
+DEF_COND_UNOP (cond_not, 512, v512hi, ~)
+DEF_COND_UNOP (cond_not, 1024, v1024hi, ~)
+DEF_COND_UNOP (cond_not, 2048, v2048hi, ~)
+
+DEF_COND_UNOP (cond_not, 4, v4si, ~)
+DEF_COND_UNOP (cond_not, 8, v8si, ~)
+DEF_COND_UNOP (cond_not, 16, v16si, ~)
+DEF_COND_UNOP (cond_not, 32, v32si, ~)
+DEF_COND_UNOP (cond_not, 64, v64si, ~)
+DEF_COND_UNOP (cond_not, 128, v128si, ~)
+DEF_COND_UNOP (cond_not, 256, v256si, ~)
+DEF_COND_UNOP (cond_not, 512, v512si, ~)
+DEF_COND_UNOP (cond_not, 1024, v1024si, ~)
+
+DEF_COND_UNOP (cond_not, 4, v4di, ~)
+DEF_COND_UNOP (cond_not, 8, v8di, ~)
+DEF_COND_UNOP (cond_not, 16, v16di, ~)
+DEF_COND_UNOP (cond_not, 32, v32di, ~)
+DEF_COND_UNOP (cond_not, 64, v64di, ~)
+DEF_COND_UNOP (cond_not, 128, v128di, ~)
+DEF_COND_UNOP (cond_not, 256, v256di, ~)
+DEF_COND_UNOP (cond_not, 512, v512di, ~)
+
+/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c
new file mode 100644
index 00000000000..3ac6203630c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_shift, 4, v4si, >>)
+DEF_COND_BINOP (cond_shift, 8, v8si, >>)
+DEF_COND_BINOP (cond_shift, 16, v16si, >>)
+DEF_COND_BINOP (cond_shift, 32, v32si, >>)
+DEF_COND_BINOP (cond_shift, 64, v64si, >>)
+DEF_COND_BINOP (cond_shift, 128, v128si, >>)
+DEF_COND_BINOP (cond_shift, 256, v256si, >>)
+DEF_COND_BINOP (cond_shift, 512, v512si, >>)
+DEF_COND_BINOP (cond_shift, 1024, v1024si, >>)
+
+DEF_COND_BINOP (cond_shift, 4, v4di, >>)
+DEF_COND_BINOP (cond_shift, 8, v8di, >>)
+DEF_COND_BINOP (cond_shift, 16, v16di, >>)
+DEF_COND_BINOP (cond_shift, 32, v32di, >>)
+DEF_COND_BINOP (cond_shift, 64, v64di, >>)
+DEF_COND_BINOP (cond_shift, 128, v128di, >>)
+DEF_COND_BINOP (cond_shift, 256, v256di, >>)
+
+DEF_COND_BINOP (cond_shift, 4, v4usi, >>)
+DEF_COND_BINOP (cond_shift, 8, v8usi, >>)
+DEF_COND_BINOP (cond_shift, 16, v16usi, >>)
+DEF_COND_BINOP (cond_shift, 32, v32usi, >>)
+DEF_COND_BINOP (cond_shift, 64, v64usi, >>)
+DEF_COND_BINOP (cond_shift, 128, v128usi, >>)
+DEF_COND_BINOP (cond_shift, 256, v256usi, >>)
+DEF_COND_BINOP (cond_shift, 512, v512usi, >>)
+DEF_COND_BINOP (cond_shift, 1024, v1024usi, >>)
+
+DEF_COND_BINOP (cond_shift, 4, v4udi, >>)
+DEF_COND_BINOP (cond_shift, 8, v8udi, >>)
+DEF_COND_BINOP (cond_shift, 16, v16udi, >>)
+DEF_COND_BINOP (cond_shift, 32, v32udi, >>)
+DEF_COND_BINOP (cond_shift, 64, v64udi, >>)
+DEF_COND_BINOP (cond_shift, 128, v128udi, >>)
+DEF_COND_BINOP (cond_shift, 256, v256udi, >>)
+
+/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 16 } } */
+/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 16 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c
new file mode 100644
index 00000000000..8c2fa470dad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_shift, 4, v4si, <<)
+DEF_COND_BINOP (cond_shift, 8, v8si, <<)
+DEF_COND_BINOP (cond_shift, 16, v16si, <<)
+DEF_COND_BINOP (cond_shift, 32, v32si, <<)
+DEF_COND_BINOP (cond_shift, 64, v64si, <<)
+DEF_COND_BINOP (cond_shift, 128, v128si, <<)
+DEF_COND_BINOP (cond_shift, 256, v256si, <<)
+DEF_COND_BINOP (cond_shift, 512, v512si, <<)
+DEF_COND_BINOP (cond_shift, 1024, v1024si, <<)
+
+DEF_COND_BINOP (cond_shift, 4, v4di, <<)
+DEF_COND_BINOP (cond_shift, 8, v8di, <<)
+DEF_COND_BINOP (cond_shift, 16, v16di, <<)
+DEF_COND_BINOP (cond_shift, 32, v32di, <<)
+DEF_COND_BINOP (cond_shift, 64, v64di, <<)
+DEF_COND_BINOP (cond_shift, 128, v128di, <<)
+DEF_COND_BINOP (cond_shift, 256, v256di, <<)
+
+DEF_COND_BINOP (cond_shift, 4, v4usi, <<)
+DEF_COND_BINOP (cond_shift, 8, v8usi, <<)
+DEF_COND_BINOP (cond_shift, 16, v16usi, <<)
+DEF_COND_BINOP (cond_shift, 32, v32usi, <<)
+DEF_COND_BINOP (cond_shift, 64, v64usi, <<)
+DEF_COND_BINOP (cond_shift, 128, v128usi, <<)
+DEF_COND_BINOP (cond_shift, 256, v256usi, <<)
+DEF_COND_BINOP (cond_shift, 512, v512usi, <<)
+DEF_COND_BINOP (cond_shift, 1024, v1024usi, <<)
+
+DEF_COND_BINOP (cond_shift, 4, v4udi, <<)
+DEF_COND_BINOP (cond_shift, 8, v8udi, <<)
+DEF_COND_BINOP (cond_shift, 16, v16udi, <<)
+DEF_COND_BINOP (cond_shift, 32, v32udi, <<)
+DEF_COND_BINOP (cond_shift, 64, v64udi, <<)
+DEF_COND_BINOP (cond_shift, 128, v128udi, <<)
+DEF_COND_BINOP (cond_shift, 256, v256udi, <<)
+
+/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 32 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c
new file mode 100644
index 00000000000..629e66cd630
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_sub, 4, v4qi, -)
+DEF_COND_BINOP (cond_sub, 8, v8qi, -)
+DEF_COND_BINOP (cond_sub, 16, v16qi, -)
+DEF_COND_BINOP (cond_sub, 32, v32qi, -)
+DEF_COND_BINOP (cond_sub, 64, v64qi, -)
+DEF_COND_BINOP (cond_sub, 128, v128qi, -)
+DEF_COND_BINOP (cond_sub, 256, v256qi, -)
+DEF_COND_BINOP (cond_sub, 512, v512qi, -)
+DEF_COND_BINOP (cond_sub, 1024, v1024qi, -)
+DEF_COND_BINOP (cond_sub, 2048, v2048qi, -)
+DEF_COND_BINOP (cond_sub, 4096, v4096qi, -)
+
+DEF_COND_BINOP (cond_sub, 4, v4hi, -)
+DEF_COND_BINOP (cond_sub, 8, v8hi, -)
+DEF_COND_BINOP (cond_sub, 16, v16hi, -)
+DEF_COND_BINOP (cond_sub, 32, v32hi, -)
+DEF_COND_BINOP (cond_sub, 64, v64hi, -)
+DEF_COND_BINOP (cond_sub, 128, v128hi, -)
+DEF_COND_BINOP (cond_sub, 256, v256hi, -)
+DEF_COND_BINOP (cond_sub, 512, v512hi, -)
+DEF_COND_BINOP (cond_sub, 1024, v1024hi, -)
+DEF_COND_BINOP (cond_sub, 2048, v2048hi, -)
+
+DEF_COND_BINOP (cond_sub, 4, v4si, -)
+DEF_COND_BINOP (cond_sub, 8, v8si, -)
+DEF_COND_BINOP (cond_sub, 16, v16si, -)
+DEF_COND_BINOP (cond_sub, 32, v32si, -)
+DEF_COND_BINOP (cond_sub, 64, v64si, -)
+DEF_COND_BINOP (cond_sub, 128, v128si, -)
+DEF_COND_BINOP (cond_sub, 256, v256si, -)
+DEF_COND_BINOP (cond_sub, 512, v512si, -)
+DEF_COND_BINOP (cond_sub, 1024, v1024si, -)
+
+DEF_COND_BINOP (cond_sub, 4, v4di, -)
+DEF_COND_BINOP (cond_sub, 8, v8di, -)
+DEF_COND_BINOP (cond_sub, 16, v16di, -)
+DEF_COND_BINOP (cond_sub, 32, v32di, -)
+DEF_COND_BINOP (cond_sub, 64, v64di, -)
+DEF_COND_BINOP (cond_sub, 128, v128di, -)
+DEF_COND_BINOP (cond_sub, 256, v256di, -)
+DEF_COND_BINOP (cond_sub, 512, v512di, -)
+
+DEF_COND_BINOP (cond_sub, 4, v4uqi, -)
+DEF_COND_BINOP (cond_sub, 8, v8uqi, -)
+DEF_COND_BINOP (cond_sub, 16, v16uqi, -)
+DEF_COND_BINOP (cond_sub, 32, v32uqi, -)
+DEF_COND_BINOP (cond_sub, 64, v64uqi, -)
+DEF_COND_BINOP (cond_sub, 128, v128uqi, -)
+DEF_COND_BINOP (cond_sub, 256, v256uqi, -)
+DEF_COND_BINOP (cond_sub, 512, v512uqi, -)
+DEF_COND_BINOP (cond_sub, 1024, v1024uqi, -)
+DEF_COND_BINOP (cond_sub, 2048, v2048uqi, -)
+DEF_COND_BINOP (cond_sub, 4096, v4096uqi, -)
+
+DEF_COND_BINOP (cond_sub, 4, v4uhi, -)
+DEF_COND_BINOP (cond_sub, 8, v8uhi, -)
+DEF_COND_BINOP (cond_sub, 16, v16uhi, -)
+DEF_COND_BINOP (cond_sub, 32, v32uhi, -)
+DEF_COND_BINOP (cond_sub, 64, v64uhi, -)
+DEF_COND_BINOP (cond_sub, 128, v128uhi, -)
+DEF_COND_BINOP (cond_sub, 256, v256uhi, -)
+DEF_COND_BINOP (cond_sub, 512, v512uhi, -)
+DEF_COND_BINOP (cond_sub, 1024, v1024uhi, -)
+DEF_COND_BINOP (cond_sub, 2048, v2048uhi, -)
+
+DEF_COND_BINOP (cond_sub, 4, v4usi, -)
+DEF_COND_BINOP (cond_sub, 8, v8usi, -)
+DEF_COND_BINOP (cond_sub, 16, v16usi, -)
+DEF_COND_BINOP (cond_sub, 32, v32usi, -)
+DEF_COND_BINOP (cond_sub, 64, v64usi, -)
+DEF_COND_BINOP (cond_sub, 128, v128usi, -)
+DEF_COND_BINOP (cond_sub, 256, v256usi, -)
+DEF_COND_BINOP (cond_sub, 512, v512usi, -)
+DEF_COND_BINOP (cond_sub, 1024, v1024usi, -)
+
+DEF_COND_BINOP (cond_sub, 4, v4udi, -)
+DEF_COND_BINOP (cond_sub, 8, v8udi, -)
+DEF_COND_BINOP (cond_sub, 16, v16udi, -)
+DEF_COND_BINOP (cond_sub, 32, v32udi, -)
+DEF_COND_BINOP (cond_sub, 64, v64udi, -)
+DEF_COND_BINOP (cond_sub, 128, v128udi, -)
+DEF_COND_BINOP (cond_sub, 256, v256udi, -)
+DEF_COND_BINOP (cond_sub, 512, v512udi, -)
+
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c
new file mode 100644
index 00000000000..385ab41d173
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_sub, 4, v4hf, -)
+DEF_COND_BINOP (cond_sub, 8, v8hf, -)
+DEF_COND_BINOP (cond_sub, 16, v16hf, -)
+DEF_COND_BINOP (cond_sub, 32, v32hf, -)
+DEF_COND_BINOP (cond_sub, 64, v64hf, -)
+DEF_COND_BINOP (cond_sub, 128, v128hf, -)
+DEF_COND_BINOP (cond_sub, 256, v256hf, -)
+DEF_COND_BINOP (cond_sub, 512, v512hf, -)
+DEF_COND_BINOP (cond_sub, 1024, v1024hf, -)
+DEF_COND_BINOP (cond_sub, 2048, v2048hf, -)
+
+DEF_COND_BINOP (cond_sub, 4, v4sf, -)
+DEF_COND_BINOP (cond_sub, 8, v8sf, -)
+DEF_COND_BINOP (cond_sub, 16, v16sf, -)
+DEF_COND_BINOP (cond_sub, 32, v32sf, -)
+DEF_COND_BINOP (cond_sub, 64, v64sf, -)
+DEF_COND_BINOP (cond_sub, 128, v128sf, -)
+DEF_COND_BINOP (cond_sub, 256, v256sf, -)
+DEF_COND_BINOP (cond_sub, 512, v512sf, -)
+DEF_COND_BINOP (cond_sub, 1024, v1024sf, -)
+
+DEF_COND_BINOP (cond_sub, 4, v4df, -)
+DEF_COND_BINOP (cond_sub, 8, v8df, -)
+DEF_COND_BINOP (cond_sub, 16, v16df, -)
+DEF_COND_BINOP (cond_sub, 32, v32df, -)
+DEF_COND_BINOP (cond_sub, 64, v64df, -)
+DEF_COND_BINOP (cond_sub, 128, v128df, -)
+DEF_COND_BINOP (cond_sub, 256, v256df, -)
+DEF_COND_BINOP (cond_sub, 512, v512df, -)
+
+/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c
new file mode 100644
index 00000000000..1bb05701773
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_BINOP (cond_xor, 4, v4qi, ^)
+DEF_COND_BINOP (cond_xor, 8, v8qi, ^)
+DEF_COND_BINOP (cond_xor, 16, v16qi, ^)
+DEF_COND_BINOP (cond_xor, 32, v32qi, ^)
+DEF_COND_BINOP (cond_xor, 64, v64qi, ^)
+DEF_COND_BINOP (cond_xor, 128, v128qi, ^)
+DEF_COND_BINOP (cond_xor, 256, v256qi, ^)
+DEF_COND_BINOP (cond_xor, 512, v512qi, ^)
+DEF_COND_BINOP (cond_xor, 1024, v1024qi, ^)
+DEF_COND_BINOP (cond_xor, 2048, v2048qi, ^)
+DEF_COND_BINOP (cond_xor, 4096, v4096qi, ^)
+
+DEF_COND_BINOP (cond_xor, 4, v4hi, ^)
+DEF_COND_BINOP (cond_xor, 8, v8hi, ^)
+DEF_COND_BINOP (cond_xor, 16, v16hi, ^)
+DEF_COND_BINOP (cond_xor, 32, v32hi, ^)
+DEF_COND_BINOP (cond_xor, 64, v64hi, ^)
+DEF_COND_BINOP (cond_xor, 128, v128hi, ^)
+DEF_COND_BINOP (cond_xor, 256, v256hi, ^)
+DEF_COND_BINOP (cond_xor, 512, v512hi, ^)
+DEF_COND_BINOP (cond_xor, 1024, v1024hi, ^)
+DEF_COND_BINOP (cond_xor, 2048, v2048hi, ^)
+
+DEF_COND_BINOP (cond_xor, 4, v4si, ^)
+DEF_COND_BINOP (cond_xor, 8, v8si, ^)
+DEF_COND_BINOP (cond_xor, 16, v16si, ^)
+DEF_COND_BINOP (cond_xor, 32, v32si, ^)
+DEF_COND_BINOP (cond_xor, 64, v64si, ^)
+DEF_COND_BINOP (cond_xor, 128, v128si, ^)
+DEF_COND_BINOP (cond_xor, 256, v256si, ^)
+DEF_COND_BINOP (cond_xor, 512, v512si, ^)
+DEF_COND_BINOP (cond_xor, 1024, v1024si, ^)
+
+DEF_COND_BINOP (cond_xor, 4, v4di, ^)
+DEF_COND_BINOP (cond_xor, 8, v8di, ^)
+DEF_COND_BINOP (cond_xor, 16, v16di, ^)
+DEF_COND_BINOP (cond_xor, 32, v32di, ^)
+DEF_COND_BINOP (cond_xor, 64, v64di, ^)
+DEF_COND_BINOP (cond_xor, 128, v128di, ^)
+DEF_COND_BINOP (cond_xor, 256, v256di, ^)
+DEF_COND_BINOP (cond_xor, 512, v512di, ^)
+
+DEF_COND_BINOP (cond_xor, 4, v4uqi, ^)
+DEF_COND_BINOP (cond_xor, 8, v8uqi, ^)
+DEF_COND_BINOP (cond_xor, 16, v16uqi, ^)
+DEF_COND_BINOP (cond_xor, 32, v32uqi, ^)
+DEF_COND_BINOP (cond_xor, 64, v64uqi, ^)
+DEF_COND_BINOP (cond_xor, 128, v128uqi, ^)
+DEF_COND_BINOP (cond_xor, 256, v256uqi, ^)
+DEF_COND_BINOP (cond_xor, 512, v512uqi, ^)
+DEF_COND_BINOP (cond_xor, 1024, v1024uqi, ^)
+DEF_COND_BINOP (cond_xor, 2048, v2048uqi, ^)
+DEF_COND_BINOP (cond_xor, 4096, v4096uqi, ^)
+
+DEF_COND_BINOP (cond_xor, 4, v4uhi, ^)
+DEF_COND_BINOP (cond_xor, 8, v8uhi, ^)
+DEF_COND_BINOP (cond_xor, 16, v16uhi, ^)
+DEF_COND_BINOP (cond_xor, 32, v32uhi, ^)
+DEF_COND_BINOP (cond_xor, 64, v64uhi, ^)
+DEF_COND_BINOP (cond_xor, 128, v128uhi, ^)
+DEF_COND_BINOP (cond_xor, 256, v256uhi, ^)
+DEF_COND_BINOP (cond_xor, 512, v512uhi, ^)
+DEF_COND_BINOP (cond_xor, 1024, v1024uhi, ^)
+DEF_COND_BINOP (cond_xor, 2048, v2048uhi, ^)
+
+DEF_COND_BINOP (cond_xor, 4, v4usi, ^)
+DEF_COND_BINOP (cond_xor, 8, v8usi, ^)
+DEF_COND_BINOP (cond_xor, 16, v16usi, ^)
+DEF_COND_BINOP (cond_xor, 32, v32usi, ^)
+DEF_COND_BINOP (cond_xor, 64, v64usi, ^)
+DEF_COND_BINOP (cond_xor, 128, v128usi, ^)
+DEF_COND_BINOP (cond_xor, 256, v256usi, ^)
+DEF_COND_BINOP (cond_xor, 512, v512usi, ^)
+DEF_COND_BINOP (cond_xor, 1024, v1024usi, ^)
+
+DEF_COND_BINOP (cond_xor, 4, v4udi, ^)
+DEF_COND_BINOP (cond_xor, 8, v8udi, ^)
+DEF_COND_BINOP (cond_xor, 16, v16udi, ^)
+DEF_COND_BINOP (cond_xor, 32, v32udi, ^)
+DEF_COND_BINOP (cond_xor, 64, v64udi, ^)
+DEF_COND_BINOP (cond_xor, 128, v128udi, ^)
+DEF_COND_BINOP (cond_xor, 256, v256udi, ^)
+DEF_COND_BINOP (cond_xor, 512, v512udi, ^)
+
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 26671b2975c..39495efe025 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -526,3 +526,73 @@ typedef double v512df __attribute__ ((vector_size (4096)));
for (int i = 0; i < NUM; ++i) \
dst[i] = src[i] % 19; \
}
+
+#define DEF_COND_UNOP(PREFIX, NUM, TYPE, OP) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE cond) \
+ { \
+ TYPE v; \
+ for (int i = 0; i < NUM; ++i) \
+ v[i] = cond[i] ? OP (a[i]) : b[i]; \
+ return v; \
+ }
+
+#define DEF_COND_BINOP(PREFIX, NUM, TYPE, OP) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \
+ { \
+ TYPE v; \
+ for (int i = 0; i < NUM; ++i) \
+ v[i] = cond[i] ? a[i] OP b[i] : c[i]; \
+ return v; \
+ }
+
+#define DEF_COND_MINMAX(PREFIX, NUM, TYPE, OP) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \
+ { \
+ TYPE v; \
+ for (int i = 0; i < NUM; ++i) \
+ v[i] = cond[i] ? ((a[i]) OP (b[i]) ? (a[i]) : (b[i])) : c[i]; \
+ return v; \
+ }
+
+#define DEF_COND_FMA_VV(PREFIX, NUM, TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \
+ { \
+ TYPE v; \
+ for (int i = 0; i < NUM; ++i) \
+ v[i] = cond[i] ? a[i] * b[i] + c[i] : b[i]; \
+ return v; \
+ }
+
+#define DEF_COND_FNMA_VV(PREFIX, NUM, TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \
+ { \
+ TYPE v; \
+ for (int i = 0; i < NUM; ++i) \
+ v[i] = cond[i] ? a[i] - b[i] * c[i] : b[i]; \
+ return v; \
+ }
+
+#define DEF_COND_FMS_VV(PREFIX, NUM, TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \
+ { \
+ TYPE v; \
+ for (int i = 0; i < NUM; ++i) \
+ v[i] = cond[i] ? a[i] * b[i] - c[i] : b[i]; \
+ return v; \
+ }
+
+#define DEF_COND_FNMS_VV(PREFIX, NUM, TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \
+ { \
+ TYPE v; \
+ for (int i = 0; i < NUM; ++i) \
+ v[i] = cond[i] ? -(a[i] * b[i]) - c[i] : b[i]; \
+ return v; \
+ }
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2023-09-26 15:12 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add VLS conditional patterns support Jeff Law
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