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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Support full coverage VLS combine support
@ 2023-09-26 15:13 Jeff Law
0 siblings, 0 replies; only message in thread
From: Jeff Law @ 2023-09-26 15:13 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7ccf013cb31ae7ffe09ebe485d7b95c6b4749366
commit 7ccf013cb31ae7ffe09ebe485d7b95c6b4749366
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Sun Sep 24 08:09:38 2023 +0800
RISC-V: Support full coverage VLS combine support
Support full coverage VLS combine support.
Committed.
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Extend VLS modes
* config/riscv/vector-iterators.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h:
* gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/narrow-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/narrow-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/narrow-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/wred-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/wred-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/wred-3.c: New test.
(cherry picked from commit e4aa1a49010fb55f3e90731464d21b05baeb6855)
Diff:
---
gcc/config/riscv/autovec-opt.md | 38 +--
gcc/config/riscv/vector-iterators.md | 287 +++++++++++++++++++++
.../riscv/rvv/autovec/vls/cond_convert-1.c | 73 ++++++
.../riscv/rvv/autovec/vls/cond_convert-10.c | 72 ++++++
.../riscv/rvv/autovec/vls/cond_convert-11.c | 54 ++++
.../riscv/rvv/autovec/vls/cond_convert-12.c | 36 +++
.../riscv/rvv/autovec/vls/cond_convert-2.c | 62 +++++
.../riscv/rvv/autovec/vls/cond_convert-3.c | 54 ++++
.../riscv/rvv/autovec/vls/cond_convert-4.c | 36 +++
.../riscv/rvv/autovec/vls/cond_convert-5.c | 72 ++++++
.../riscv/rvv/autovec/vls/cond_convert-6.c | 54 ++++
.../riscv/rvv/autovec/vls/cond_convert-7.c | 36 +++
.../riscv/rvv/autovec/vls/cond_convert-8.c | 54 ++++
.../riscv/rvv/autovec/vls/cond_convert-9.c | 22 ++
.../riscv/rvv/autovec/vls/cond_copysign-1.c | 50 ++++
.../gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c | 73 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c | 55 ++++
.../gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c | 37 +++
.../gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c | 37 +++
.../gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c | 28 ++
.../gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c | 81 ++++++
.../riscv/rvv/autovec/vls/cond_narrow-1.c | 61 +++++
.../riscv/rvv/autovec/vls/cond_narrow-2.c | 41 +++
.../riscv/rvv/autovec/vls/cond_trunc-1.c | 72 ++++++
.../riscv/rvv/autovec/vls/cond_trunc-2.c | 54 ++++
.../riscv/rvv/autovec/vls/cond_trunc-3.c | 36 +++
.../riscv/rvv/autovec/vls/cond_trunc-4.c | 37 +++
.../riscv/rvv/autovec/vls/cond_trunc-5.c | 28 ++
.../gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c | 79 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c | 39 +++
.../gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c | 79 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c | 39 +++
.../gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c | 79 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c | 39 +++
.../gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c | 39 +++
.../riscv/rvv/autovec/vls/cond_wfnma-1.c | 39 +++
.../gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c | 79 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c | 39 +++
.../gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c | 49 ++++
.../gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c | 79 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c | 39 +++
.../gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c | 79 ++++++
.../gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c | 39 +++
.../gcc.target/riscv/rvv/autovec/vls/def.h | 154 +++++++++++
.../gcc.target/riscv/rvv/autovec/vls/narrow-1.c | 49 ++++
.../gcc.target/riscv/rvv/autovec/vls/narrow-2.c | 28 ++
.../gcc.target/riscv/rvv/autovec/vls/narrow-3.c | 28 ++
.../gcc.target/riscv/rvv/autovec/vls/wred-1.c | 80 ++++++
.../gcc.target/riscv/rvv/autovec/vls/wred-2.c | 38 +++
.../gcc.target/riscv/rvv/autovec/vls/wred-3.c | 19 ++
50 files changed, 2852 insertions(+), 19 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 6c6609d24bb..d0f8b3cde4e 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -262,7 +262,7 @@
(if_then_else:<VCONVERT>
(match_operand:<VM> 1 "register_operand")
(any_fix:<VCONVERT>
- (match_operand:VF 2 "register_operand"))
+ (match_operand:V_VLSF 2 "register_operand"))
(match_operand:<VCONVERT> 3 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
@@ -279,12 +279,12 @@
;; Combine convert(INT->FP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><vconvert><mode>"
- [(set (match_operand:VF 0 "register_operand")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (if_then_else:V_VLSF
(match_operand:<VM> 1 "register_operand")
- (any_float:VF
+ (any_float:V_VLSF
(match_operand:<VCONVERT> 2 "register_operand"))
- (match_operand:VF 3 "register_operand")))]
+ (match_operand:V_VLSF 3 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -321,12 +321,12 @@
;; Combine convert(INT->2xFP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><vnconvert><mode>"
- [(set (match_operand:VF 0 "register_operand")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (if_then_else:V_VLSF
(match_operand:<VM> 1 "register_operand")
- (any_float:VF
+ (any_float:V_VLSF
(match_operand:<VNCONVERT> 2 "register_operand"))
- (match_operand:VF 3 "register_operand")))]
+ (match_operand:V_VLSF 3 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -346,7 +346,7 @@
(if_then_else:<VNCONVERT>
(match_operand:<VM> 1 "register_operand")
(any_fix:<VNCONVERT>
- (match_operand:VF 2 "register_operand"))
+ (match_operand:V_VLSF 2 "register_operand"))
(match_operand:<VNCONVERT> 3 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
@@ -384,13 +384,13 @@
;; Combine vfsgnj.vv + vcond_mask
(define_insn_and_split "*cond_copysign<mode>"
- [(set (match_operand:VF 0 "register_operand")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (if_then_else:V_VLSF
(match_operand:<VM> 1 "register_operand")
- (unspec:VF
- [(match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")] UNSPEC_VCOPYSIGN)
- (match_operand:VF 4 "register_operand")))]
+ (unspec:V_VLSF
+ [(match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")] UNSPEC_VCOPYSIGN)
+ (match_operand:V_VLSF 4 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -760,8 +760,8 @@
[(set (match_operand:<V_DOUBLE_EXTEND_VEL> 0 "register_operand")
(unspec:<V_DOUBLE_EXTEND_VEL> [
(float_extend:<V_DOUBLE_EXTEND>
- (match_operand:VF_HS_NO_M8 2 "register_operand"))
- (match_operand:<V_DOUBLE_EXTEND_VEL> 1 "register_operand")
+ (match_operand:VF_HS_NO_M8 1 "register_operand"))
+ (match_operand:<V_DOUBLE_EXTEND_VEL> 2 "register_operand")
] UNSPEC_REDUC_SUM_ORDERED))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
@@ -770,7 +770,7 @@
{
riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
riscv_vector::REDUCE_OP_FRM_DYN,
- operands, operands[1]);
+ operands, operands[2]);
DONE;
}
[(set_attr "type" "vector")])
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index aa9bcc75862..b6cd872eb42 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -731,6 +731,43 @@
RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
+
+ (V1QI "TARGET_VECTOR_VLS")
+ (V2QI "TARGET_VECTOR_VLS")
+ (V4QI "TARGET_VECTOR_VLS")
+ (V8QI "TARGET_VECTOR_VLS")
+ (V16QI "TARGET_VECTOR_VLS")
+ (V32QI "TARGET_VECTOR_VLS")
+ (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+ (V1HI "TARGET_VECTOR_VLS")
+ (V2HI "TARGET_VECTOR_VLS")
+ (V4HI "TARGET_VECTOR_VLS")
+ (V8HI "TARGET_VECTOR_VLS")
+ (V16HI "TARGET_VECTOR_VLS")
+ (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+ (V1SI "TARGET_VECTOR_VLS")
+ (V2SI "TARGET_VECTOR_VLS")
+ (V4SI "TARGET_VECTOR_VLS")
+ (V8SI "TARGET_VECTOR_VLS")
+ (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
])
(define_mode_iterator VI_QHS_NO_M8 [
@@ -739,6 +776,40 @@
RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
+
+ (V1QI "TARGET_VECTOR_VLS")
+ (V2QI "TARGET_VECTOR_VLS")
+ (V4QI "TARGET_VECTOR_VLS")
+ (V8QI "TARGET_VECTOR_VLS")
+ (V16QI "TARGET_VECTOR_VLS")
+ (V32QI "TARGET_VECTOR_VLS")
+ (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V1HI "TARGET_VECTOR_VLS")
+ (V2HI "TARGET_VECTOR_VLS")
+ (V4HI "TARGET_VECTOR_VLS")
+ (V8HI "TARGET_VECTOR_VLS")
+ (V16HI "TARGET_VECTOR_VLS")
+ (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V1SI "TARGET_VECTOR_VLS")
+ (V2SI "TARGET_VECTOR_VLS")
+ (V4SI "TARGET_VECTOR_VLS")
+ (V8SI "TARGET_VECTOR_VLS")
+ (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
])
(define_mode_iterator VF_HS [
@@ -748,6 +819,30 @@
(RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
(RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+
+ (V1HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+ (V2HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+ (V4HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+ (V8HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+ (V16HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+ (V32HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
+ (V64HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+ (V128HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
+ (V256HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
+ (V512HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
+ (V1024HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
+ (V2048HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096")
+ (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+ (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+ (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+ (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+ (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
+ (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
+ (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
+ (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
+ (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
+ (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
])
(define_mode_iterator VF_HS_NO_M8 [
@@ -760,6 +855,28 @@
(RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
(RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
(RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+
+ (V1HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+ (V2HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+ (V4HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+ (V8HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+ (V16HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
+ (V32HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
+ (V64HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+ (V128HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
+ (V256HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
+ (V512HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
+ (V1024HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
+ (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+ (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+ (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+ (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
+ (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
+ (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
+ (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
+ (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
+ (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
])
(define_mode_iterator VF_HS_M8 [
@@ -1583,6 +1700,66 @@
(RVVM8HF "RVVM1SF") (RVVM4HF "RVVM1SF") (RVVM2HF "RVVM1SF") (RVVM1HF "RVVM1SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVM1SF")
(RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF")
+
+ (V1QI "RVVM1HI")
+ (V2QI "RVVM1HI")
+ (V4QI "RVVM1HI")
+ (V8QI "RVVM1HI")
+ (V16QI "RVVM1HI")
+ (V32QI "RVVM1HI")
+ (V64QI "RVVM1HI")
+ (V128QI "RVVM1HI")
+ (V256QI "RVVM1HI")
+ (V512QI "RVVM1HI")
+ (V1024QI "RVVM1HI")
+ (V2048QI "RVVM1HI")
+ (V4096QI "RVVM1HI")
+ (V1HI "RVVM1SI")
+ (V2HI "RVVM1SI")
+ (V4HI "RVVM1SI")
+ (V8HI "RVVM1SI")
+ (V16HI "RVVM1SI")
+ (V32HI "RVVM1SI")
+ (V64HI "RVVM1SI")
+ (V128HI "RVVM1SI")
+ (V256HI "RVVM1SI")
+ (V512HI "RVVM1SI")
+ (V1024HI "RVVM1SI")
+ (V2048HI "RVVM1SI")
+ (V1SI "RVVM1DI")
+ (V2SI "RVVM1DI")
+ (V4SI "RVVM1DI")
+ (V8SI "RVVM1DI")
+ (V16SI "RVVM1DI")
+ (V32SI "RVVM1DI")
+ (V64SI "RVVM1DI")
+ (V128SI "RVVM1DI")
+ (V256SI "RVVM1DI")
+ (V512SI "RVVM1DI")
+ (V1024SI "RVVM1DI")
+ (V1HF "RVVM1SF")
+ (V2HF "RVVM1SF")
+ (V4HF "RVVM1SF")
+ (V8HF "RVVM1SF")
+ (V16HF "RVVM1SF")
+ (V32HF "RVVM1SF")
+ (V64HF "RVVM1SF")
+ (V128HF "RVVM1SF")
+ (V256HF "RVVM1SF")
+ (V512HF "RVVM1SF")
+ (V1024HF "RVVM1SF")
+ (V2048HF "RVVM1SF")
+ (V1SF "RVVM1DF")
+ (V2SF "RVVM1DF")
+ (V4SF "RVVM1DF")
+ (V8SF "RVVM1DF")
+ (V16SF "RVVM1DF")
+ (V32SF "RVVM1DF")
+ (V64SF "RVVM1DF")
+ (V128SF "RVVM1DF")
+ (V256SF "RVVM1DF")
+ (V512SF "RVVM1DF")
+ (V1024SF "RVVM1DF")
])
(define_int_iterator ANY_REDUC [
@@ -2051,6 +2228,61 @@
(RVVM4HF "SF") (RVVM2HF "SF") (RVVM1HF "SF") (RVVMF2HF "SF") (RVVMF4HF "SF")
(RVVM4SF "DF") (RVVM2SF "DF") (RVVM1SF "DF") (RVVMF2SF "DF")
+
+ (V1QI "HI")
+ (V2QI "HI")
+ (V4QI "HI")
+ (V8QI "HI")
+ (V16QI "HI")
+ (V32QI "HI")
+ (V64QI "HI")
+ (V128QI "HI")
+ (V256QI "HI")
+ (V512QI "HI")
+ (V1024QI "HI")
+ (V2048QI "HI")
+ (V1HI "SI")
+ (V2HI "SI")
+ (V4HI "SI")
+ (V8HI "SI")
+ (V16HI "SI")
+ (V32HI "SI")
+ (V64HI "SI")
+ (V128HI "SI")
+ (V256HI "SI")
+ (V512HI "SI")
+ (V1024HI "SI")
+ (V1SI "SI")
+ (V2SI "SI")
+ (V4SI "SI")
+ (V8SI "SI")
+ (V16SI "SI")
+ (V32SI "SI")
+ (V64SI "SI")
+ (V128SI "SI")
+ (V256SI "SI")
+ (V512SI "SI")
+ (V1HF "SF")
+ (V2HF "SF")
+ (V4HF "SF")
+ (V8HF "SF")
+ (V16HF "SF")
+ (V32HF "SF")
+ (V64HF "SF")
+ (V128HF "SF")
+ (V256HF "SF")
+ (V512HF "SF")
+ (V1024HF "SF")
+ (V1SF "DF")
+ (V2SF "DF")
+ (V4SF "DF")
+ (V8SF "DF")
+ (V16SF "DF")
+ (V32SF "DF")
+ (V64SF "DF")
+ (V128SF "DF")
+ (V256SF "DF")
+ (V512SF "DF")
])
(define_mode_attr vel [
@@ -2443,6 +2675,61 @@
(RVVM4HF "RVVM8SF") (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVMF2SF")
(RVVM4SF "RVVM8DF") (RVVM2SF "RVVM4DF") (RVVM1SF "RVVM2DF") (RVVMF2SF "RVVM1DF")
+
+ (V1QI "V1HI")
+ (V2QI "V2HI")
+ (V4QI "V4HI")
+ (V8QI "V8HI")
+ (V16QI "V16HI")
+ (V32QI "V32HI")
+ (V64QI "V64HI")
+ (V128QI "V128HI")
+ (V256QI "V256HI")
+ (V512QI "V512HI")
+ (V1024QI "V1024HI")
+ (V2048QI "V2048HI")
+ (V1HI "V1SI")
+ (V2HI "V2SI")
+ (V4HI "V4SI")
+ (V8HI "V8SI")
+ (V16HI "V16SI")
+ (V32HI "V32SI")
+ (V64HI "V64SI")
+ (V128HI "V128SI")
+ (V256HI "V256SI")
+ (V512HI "V512SI")
+ (V1024HI "V1024SI")
+ (V1SI "V1SI")
+ (V2SI "V2SI")
+ (V4SI "V4SI")
+ (V8SI "V8SI")
+ (V16SI "V16SI")
+ (V32SI "V32SI")
+ (V64SI "V64SI")
+ (V128SI "V128SI")
+ (V256SI "V256SI")
+ (V512SI "V512SI")
+ (V1HF "V1SF")
+ (V2HF "V2SF")
+ (V4HF "V4SF")
+ (V8HF "V8SF")
+ (V16HF "V16SF")
+ (V32HF "V32SF")
+ (V64HF "V64SF")
+ (V128HF "V128SF")
+ (V256HF "V256SF")
+ (V512HF "V512SF")
+ (V1024HF "V1024SF")
+ (V1SF "V1DF")
+ (V2SF "V2DF")
+ (V4SF "V4DF")
+ (V8SF "V8DF")
+ (V16SF "V16DF")
+ (V32SF "V32DF")
+ (V64SF "V64DF")
+ (V128SF "V128DF")
+ (V256SF "V256DF")
+ (V512SF "V512DF")
])
(define_mode_attr V_DOUBLE_TRUNC [
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c
new file mode 100644
index 00000000000..3baf5cfff07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 4)
+DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 16)
+DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 32)
+DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 64)
+DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 128)
+DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 256)
+DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 512)
+DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 1024)
+
+DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 4)
+DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 16)
+DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 32)
+DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 64)
+DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 128)
+DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 256)
+DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 512)
+DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 1024)
+
+DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 4)
+DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 16)
+DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 32)
+DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 64)
+DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 128)
+DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 256)
+DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 512)
+
+DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 4)
+DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 16)
+DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 32)
+DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 64)
+DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 128)
+DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 256)
+DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 512)
+DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 1024)
+
+DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 4)
+DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 16)
+DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 32)
+DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 64)
+DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 128)
+DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 256)
+DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 512)
+DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 1024)
+
+DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 4)
+DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 16)
+DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 32)
+DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 64)
+DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 128)
+DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 256)
+DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 512)
+
+/* { dg-final { scan-assembler-times {vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 23 } } */
+/* { dg-final { scan-assembler-times {vfcvt\.rtz\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 23 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c
new file mode 100644
index 00000000000..e56dc33212d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c
@@ -0,0 +1,72 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 4)
+DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 16)
+DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 32)
+DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 64)
+DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 128)
+DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 256)
+DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 512)
+DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 1024)
+
+DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 4)
+DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 16)
+DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 32)
+DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 64)
+DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 128)
+DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 256)
+DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 512)
+DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 1024)
+
+DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 4)
+DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 16)
+DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 32)
+DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 64)
+DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 128)
+DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 256)
+DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 512)
+DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 1024)
+
+DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 4)
+DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 16)
+DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 32)
+DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 64)
+DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 128)
+DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 256)
+DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 512)
+DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 1024)
+
+DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 4)
+DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 16)
+DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 32)
+DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 64)
+DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 128)
+DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 256)
+DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 512)
+
+DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 4)
+DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 16)
+DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 32)
+DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 64)
+DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 128)
+DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 256)
+DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 512)
+
+/* { dg-final { scan-assembler-times {vfncvt\.rtz\.xu?\.f\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 46 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
new file mode 100644
index 00000000000..41ec468bf3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 4)
+DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 16)
+DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 32)
+DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 64)
+DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 128)
+DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 256)
+DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 512)
+DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 1024)
+
+DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 4)
+DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 16)
+DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 32)
+DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 64)
+DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 128)
+DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 256)
+DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 512)
+DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 1024)
+
+DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 4)
+DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 16)
+DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 32)
+DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 64)
+DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 128)
+DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 256)
+DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 512)
+
+DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 4)
+DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 16)
+DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 32)
+DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 64)
+DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 128)
+DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 256)
+DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 512)
+
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
new file mode 100644
index 00000000000..c2cb8bfde1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 4)
+DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 16)
+DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 32)
+DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 64)
+DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 128)
+DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 256)
+DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 512)
+
+DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 4)
+DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 16)
+DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 32)
+DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 64)
+DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 128)
+DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 256)
+DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 512)
+
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c
new file mode 100644
index 00000000000..beecdf43916
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fcvt, si, sf, float, 16)
+DEF_COND_FP_CONVERT (fcvt, si, sf, float, 32)
+DEF_COND_FP_CONVERT (fcvt, si, sf, float, 64)
+DEF_COND_FP_CONVERT (fcvt, si, sf, float, 128)
+DEF_COND_FP_CONVERT (fcvt, si, sf, float, 256)
+DEF_COND_FP_CONVERT (fcvt, si, sf, float, 512)
+DEF_COND_FP_CONVERT (fcvt, si, sf, float, 1024)
+
+DEF_COND_FP_CONVERT (fcvt, di, df, double, 4)
+DEF_COND_FP_CONVERT (fcvt, di, df, double, 16)
+DEF_COND_FP_CONVERT (fcvt, di, df, double, 32)
+DEF_COND_FP_CONVERT (fcvt, di, df, double, 64)
+DEF_COND_FP_CONVERT (fcvt, di, df, double, 128)
+DEF_COND_FP_CONVERT (fcvt, di, df, double, 256)
+DEF_COND_FP_CONVERT (fcvt, di, df, double, 512)
+
+DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 4)
+DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 16)
+DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 32)
+DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 64)
+DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 128)
+DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 256)
+DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 512)
+DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 1024)
+
+DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 4)
+DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 16)
+DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 32)
+DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 64)
+DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 128)
+DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 256)
+DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 512)
+DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 1024)
+
+DEF_COND_FP_CONVERT (fcvt, udi, df, double, 4)
+DEF_COND_FP_CONVERT (fcvt, udi, df, double, 16)
+DEF_COND_FP_CONVERT (fcvt, udi, df, double, 32)
+DEF_COND_FP_CONVERT (fcvt, udi, df, double, 64)
+DEF_COND_FP_CONVERT (fcvt, udi, df, double, 128)
+DEF_COND_FP_CONVERT (fcvt, udi, df, double, 256)
+DEF_COND_FP_CONVERT (fcvt, udi, df, double, 512)
+
+/* { dg-final { scan-assembler-times {vfcvt\.f\.xu?\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 37 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c
new file mode 100644
index 00000000000..f71236b0385
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 4)
+DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 16)
+DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 32)
+DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 64)
+DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 128)
+DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 256)
+DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 512)
+DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 1024)
+
+DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 4)
+DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 16)
+DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 32)
+DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 64)
+DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 128)
+DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 256)
+DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 512)
+DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 1024)
+
+DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 4)
+DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 16)
+DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 32)
+DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 64)
+DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 128)
+DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 256)
+DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 512)
+
+DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 4)
+DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 16)
+DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 32)
+DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 64)
+DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 128)
+DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 256)
+DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 512)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.xu?\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c
new file mode 100644
index 00000000000..fa5780cc4da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 4)
+DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 16)
+DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 32)
+DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 64)
+DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 128)
+DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 256)
+DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 512)
+
+DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 4)
+DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 16)
+DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 32)
+DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 64)
+DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 128)
+DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 256)
+DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 512)
+
+/* { dg-final { scan-assembler-times {vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c
new file mode 100644
index 00000000000..696e17cb29d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c
@@ -0,0 +1,72 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 4)
+DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 16)
+DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 32)
+DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 64)
+DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 128)
+DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 256)
+DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 512)
+DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 1024)
+
+DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 4)
+DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 16)
+DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 32)
+DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 64)
+DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 128)
+DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 256)
+DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 512)
+DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 1024)
+
+DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 4)
+DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 16)
+DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 32)
+DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 64)
+DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 128)
+DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 256)
+DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 512)
+DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 1024)
+
+DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 4)
+DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 16)
+DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 32)
+DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 64)
+DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 128)
+DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 256)
+DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 512)
+DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 1024)
+
+DEF_COND_FP_CONVERT (fwcvt, si, df, double, 4)
+DEF_COND_FP_CONVERT (fwcvt, si, df, double, 16)
+DEF_COND_FP_CONVERT (fwcvt, si, df, double, 32)
+DEF_COND_FP_CONVERT (fwcvt, si, df, double, 64)
+DEF_COND_FP_CONVERT (fwcvt, si, df, double, 128)
+DEF_COND_FP_CONVERT (fwcvt, si, df, double, 256)
+DEF_COND_FP_CONVERT (fwcvt, si, df, double, 512)
+
+DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 4)
+DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 16)
+DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 32)
+DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 64)
+DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 128)
+DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 256)
+DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 512)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu?\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 46 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c
new file mode 100644
index 00000000000..a830777b9ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 4)
+DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 16)
+DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 32)
+DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 64)
+DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 128)
+DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 256)
+DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 512)
+DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 1024)
+
+DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 4)
+DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 16)
+DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 32)
+DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 64)
+DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 128)
+DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 256)
+DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 512)
+DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 1024)
+
+DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 4)
+DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 16)
+DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 32)
+DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 64)
+DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 128)
+DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 256)
+DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 512)
+
+DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 4)
+DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 16)
+DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 32)
+DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 64)
+DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 128)
+DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 256)
+DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 512)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu?\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c
new file mode 100644
index 00000000000..6f56cb6c2fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 4)
+DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 16)
+DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 32)
+DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 64)
+DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 128)
+DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 256)
+DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 512)
+
+DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 4)
+DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 16)
+DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 32)
+DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 64)
+DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 128)
+DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 256)
+DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 512)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu?\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c
new file mode 100644
index 00000000000..62cc7a3343e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 4)
+DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 16)
+DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 32)
+DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 64)
+DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 128)
+DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 256)
+DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 512)
+DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 1024)
+
+DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 4)
+DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 16)
+DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 32)
+DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 64)
+DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 128)
+DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 256)
+DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 512)
+DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 1024)
+
+DEF_COND_FP_CONVERT (fncvt, di, sf, float, 4)
+DEF_COND_FP_CONVERT (fncvt, di, sf, float, 16)
+DEF_COND_FP_CONVERT (fncvt, di, sf, float, 32)
+DEF_COND_FP_CONVERT (fncvt, di, sf, float, 64)
+DEF_COND_FP_CONVERT (fncvt, di, sf, float, 128)
+DEF_COND_FP_CONVERT (fncvt, di, sf, float, 256)
+DEF_COND_FP_CONVERT (fncvt, di, sf, float, 512)
+
+DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 4)
+DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 16)
+DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 32)
+DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 64)
+DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 128)
+DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 256)
+DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 512)
+
+/* { dg-final { scan-assembler-times {vfncvt\.f\.xu?\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c
new file mode 100644
index 00000000000..14ae1a3fe68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 4)
+DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 16)
+DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 32)
+DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 64)
+DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 128)
+DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 256)
+DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 512)
+
+DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 4)
+DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 16)
+DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 32)
+DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 64)
+DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 128)
+DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 256)
+DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 512)
+
+/* TODO: Currently, we can't vectorize DI -> HF. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c
new file mode 100644
index 00000000000..55191582d08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CALL (cond_copysign, 4, v4hf, __builtin_copysignf16)
+DEF_COND_CALL (cond_copysign, 8, v8hf, __builtin_copysignf16)
+DEF_COND_CALL (cond_copysign, 16, v16hf, __builtin_copysignf16)
+DEF_COND_CALL (cond_copysign, 32, v32hf, __builtin_copysignf16)
+DEF_COND_CALL (cond_copysign, 64, v64hf, __builtin_copysignf16)
+DEF_COND_CALL (cond_copysign, 128, v128hf, __builtin_copysignf16)
+DEF_COND_CALL (cond_copysign, 256, v256hf, __builtin_copysignf16)
+DEF_COND_CALL (cond_copysign, 512, v512hf, __builtin_copysignf16)
+DEF_COND_CALL (cond_copysign, 1024, v1024hf, __builtin_copysignf16)
+DEF_COND_CALL (cond_copysign, 2048, v2048hf, __builtin_copysignf16)
+
+DEF_COND_CALL (cond_copysign, 4, v4sf, __builtin_copysignf)
+DEF_COND_CALL (cond_copysign, 8, v8sf, __builtin_copysignf)
+DEF_COND_CALL (cond_copysign, 16, v16sf, __builtin_copysignf)
+DEF_COND_CALL (cond_copysign, 32, v32sf, __builtin_copysignf)
+DEF_COND_CALL (cond_copysign, 64, v64sf, __builtin_copysignf)
+DEF_COND_CALL (cond_copysign, 128, v128sf, __builtin_copysignf)
+DEF_COND_CALL (cond_copysign, 256, v256sf, __builtin_copysignf)
+DEF_COND_CALL (cond_copysign, 512, v512sf, __builtin_copysignf)
+DEF_COND_CALL (cond_copysign, 1024, v1024sf, __builtin_copysignf)
+
+DEF_COND_CALL (cond_copysign, 4, v4df, __builtin_copysign)
+DEF_COND_CALL (cond_copysign, 8, v8df, __builtin_copysign)
+DEF_COND_CALL (cond_copysign, 16, v16df, __builtin_copysign)
+DEF_COND_CALL (cond_copysign, 32, v32df, __builtin_copysign)
+DEF_COND_CALL (cond_copysign, 64, v64df, __builtin_copysign)
+DEF_COND_CALL (cond_copysign, 128, v128df, __builtin_copysign)
+DEF_COND_CALL (cond_copysign, 256, v256df, __builtin_copysign)
+DEF_COND_CALL (cond_copysign, 512, v512df, __builtin_copysign)
+
+/* { dg-final { scan-assembler-times {vfsgnj\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c
new file mode 100644
index 00000000000..c356cf512b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CONVERT (sext, v4qi, v4hi, 4)
+DEF_COND_CONVERT (sext, v16qi, v16hi, 16)
+DEF_COND_CONVERT (sext, v32qi, v32hi, 32)
+DEF_COND_CONVERT (sext, v64qi, v64hi, 64)
+DEF_COND_CONVERT (sext, v128qi, v128hi, 128)
+DEF_COND_CONVERT (sext, v256qi, v256hi, 256)
+DEF_COND_CONVERT (sext, v512qi, v512hi, 512)
+DEF_COND_CONVERT (sext, v1024qi, v1024hi, 1024)
+
+DEF_COND_CONVERT (sext, v4hi, v4si, 4)
+DEF_COND_CONVERT (sext, v16hi, v16si, 16)
+DEF_COND_CONVERT (sext, v32hi, v32si, 32)
+DEF_COND_CONVERT (sext, v64hi, v64si, 64)
+DEF_COND_CONVERT (sext, v128hi, v128si, 128)
+DEF_COND_CONVERT (sext, v256hi, v256si, 256)
+DEF_COND_CONVERT (sext, v512hi, v512si, 512)
+DEF_COND_CONVERT (sext, v1024hi, v1024si, 1024)
+
+DEF_COND_CONVERT (sext, v4si, v4di, 4)
+DEF_COND_CONVERT (sext, v16si, v16di, 16)
+DEF_COND_CONVERT (sext, v32si, v32di, 32)
+DEF_COND_CONVERT (sext, v64si, v64di, 64)
+DEF_COND_CONVERT (sext, v128si, v128di, 128)
+DEF_COND_CONVERT (sext, v256si, v256di, 256)
+DEF_COND_CONVERT (sext, v512si, v512di, 512)
+
+DEF_COND_CONVERT (zext, v4uqi, v4uhi, 4)
+DEF_COND_CONVERT (zext, v16uqi, v16uhi, 16)
+DEF_COND_CONVERT (zext, v32uqi, v32uhi, 32)
+DEF_COND_CONVERT (zext, v64uqi, v64uhi, 64)
+DEF_COND_CONVERT (zext, v128uqi, v128uhi, 128)
+DEF_COND_CONVERT (zext, v256uqi, v256uhi, 256)
+DEF_COND_CONVERT (zext, v512uqi, v512uhi, 512)
+DEF_COND_CONVERT (zext, v1024uqi, v1024uhi, 1024)
+
+DEF_COND_CONVERT (zext, v4uhi, v4usi, 4)
+DEF_COND_CONVERT (zext, v16uhi, v16usi, 16)
+DEF_COND_CONVERT (zext, v32uhi, v32usi, 32)
+DEF_COND_CONVERT (zext, v64uhi, v64usi, 64)
+DEF_COND_CONVERT (zext, v128uhi, v128usi, 128)
+DEF_COND_CONVERT (zext, v256uhi, v256usi, 256)
+DEF_COND_CONVERT (zext, v512uhi, v512usi, 512)
+DEF_COND_CONVERT (zext, v1024uhi, v1024usi, 1024)
+
+DEF_COND_CONVERT (zext, v4usi, v4udi, 4)
+DEF_COND_CONVERT (zext, v16usi, v16udi, 16)
+DEF_COND_CONVERT (zext, v32usi, v32udi, 32)
+DEF_COND_CONVERT (zext, v64usi, v64udi, 64)
+DEF_COND_CONVERT (zext, v128usi, v128udi, 128)
+DEF_COND_CONVERT (zext, v256usi, v256udi, 256)
+DEF_COND_CONVERT (zext, v512usi, v512udi, 512)
+
+/* { dg-final { scan-assembler-times {vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 23 } } */
+/* { dg-final { scan-assembler-times {vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 23 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c
new file mode 100644
index 00000000000..02bdf656cf8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CONVERT (sext, v4qi, v4si, 4)
+DEF_COND_CONVERT (sext, v16qi, v16si, 16)
+DEF_COND_CONVERT (sext, v32qi, v32si, 32)
+DEF_COND_CONVERT (sext, v64qi, v64si, 64)
+DEF_COND_CONVERT (sext, v128qi, v128si, 128)
+DEF_COND_CONVERT (sext, v256qi, v256si, 256)
+DEF_COND_CONVERT (sext, v512qi, v512si, 512)
+DEF_COND_CONVERT (sext, v1024qi, v1024si, 1024)
+
+DEF_COND_CONVERT (sext, v4hi, v4di, 4)
+DEF_COND_CONVERT (sext, v16hi, v16di, 16)
+DEF_COND_CONVERT (sext, v32hi, v32di, 32)
+DEF_COND_CONVERT (sext, v64hi, v64di, 64)
+DEF_COND_CONVERT (sext, v128hi, v128di, 128)
+DEF_COND_CONVERT (sext, v256hi, v256di, 256)
+DEF_COND_CONVERT (sext, v512hi, v512di, 512)
+
+DEF_COND_CONVERT (zext, v4uqi, v4usi, 4)
+DEF_COND_CONVERT (zext, v16uqi, v16usi, 16)
+DEF_COND_CONVERT (zext, v32uqi, v32usi, 32)
+DEF_COND_CONVERT (zext, v64uqi, v64usi, 64)
+DEF_COND_CONVERT (zext, v128uqi, v128usi, 128)
+DEF_COND_CONVERT (zext, v256uqi, v256usi, 256)
+DEF_COND_CONVERT (zext, v512uqi, v512usi, 512)
+DEF_COND_CONVERT (zext, v1024uqi, v1024usi, 1024)
+
+DEF_COND_CONVERT (zext, v4uhi, v4udi, 4)
+DEF_COND_CONVERT (zext, v16uhi, v16udi, 16)
+DEF_COND_CONVERT (zext, v32uhi, v32udi, 32)
+DEF_COND_CONVERT (zext, v64uhi, v64udi, 64)
+DEF_COND_CONVERT (zext, v128uhi, v128udi, 128)
+DEF_COND_CONVERT (zext, v256uhi, v256udi, 256)
+DEF_COND_CONVERT (zext, v512uhi, v512udi, 512)
+
+/* { dg-final { scan-assembler-times {vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 15 } } */
+/* { dg-final { scan-assembler-times {vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 15 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c
new file mode 100644
index 00000000000..2db3ea2c8ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CONVERT (sext, v4qi, v4di, 4)
+DEF_COND_CONVERT (sext, v16qi, v16di, 16)
+DEF_COND_CONVERT (sext, v32qi, v32di, 32)
+DEF_COND_CONVERT (sext, v64qi, v64di, 64)
+DEF_COND_CONVERT (sext, v128qi, v128di, 128)
+DEF_COND_CONVERT (sext, v256qi, v256di, 256)
+DEF_COND_CONVERT (sext, v512qi, v512di, 512)
+
+DEF_COND_CONVERT (zext, v4uqi, v4udi, 4)
+DEF_COND_CONVERT (zext, v16uqi, v16udi, 16)
+DEF_COND_CONVERT (zext, v32uqi, v32udi, 32)
+DEF_COND_CONVERT (zext, v64uqi, v64udi, 64)
+DEF_COND_CONVERT (zext, v128uqi, v128udi, 128)
+DEF_COND_CONVERT (zext, v256uqi, v256udi, 256)
+DEF_COND_CONVERT (zext, v512uqi, v512udi, 512)
+
+/* { dg-final { scan-assembler-times {vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 7 } } */
+/* { dg-final { scan-assembler-times {vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 7 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c
new file mode 100644
index 00000000000..192722c3289
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CONVERT (fwcvt, v4hf, v4sf, 4)
+DEF_COND_CONVERT (fwcvt, v16hf, v16sf, 16)
+DEF_COND_CONVERT (fwcvt, v32hf, v32sf, 32)
+DEF_COND_CONVERT (fwcvt, v64hf, v64sf, 64)
+DEF_COND_CONVERT (fwcvt, v128hf, v128sf, 128)
+DEF_COND_CONVERT (fwcvt, v256hf, v256sf, 256)
+DEF_COND_CONVERT (fwcvt, v512hf, v512sf, 512)
+DEF_COND_CONVERT (fwcvt, v1024hf, v1024sf, 1024)
+
+DEF_COND_CONVERT (fwcvt, v4sf, v4df, 4)
+DEF_COND_CONVERT (fwcvt, v16sf, v16df, 16)
+DEF_COND_CONVERT (fwcvt, v32sf, v32df, 32)
+DEF_COND_CONVERT (fwcvt, v64sf, v64df, 64)
+DEF_COND_CONVERT (fwcvt, v128sf, v128df, 128)
+DEF_COND_CONVERT (fwcvt, v256sf, v256df, 256)
+DEF_COND_CONVERT (fwcvt, v512sf, v512df, 512)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 15 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c
new file mode 100644
index 00000000000..96ba993a24f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CONVERT (fwcvt, v4hf, v4df, 4)
+DEF_COND_CONVERT (fwcvt, v16hf, v16df, 16)
+DEF_COND_CONVERT (fwcvt, v32hf, v32df, 32)
+DEF_COND_CONVERT (fwcvt, v64hf, v64df, 64)
+DEF_COND_CONVERT (fwcvt, v128hf, v128df, 128)
+DEF_COND_CONVERT (fwcvt, v256hf, v256df, 256)
+DEF_COND_CONVERT (fwcvt, v512hf, v512df, 512)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 7 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c
new file mode 100644
index 00000000000..ffa6458a9e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c
@@ -0,0 +1,81 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_MULH (cond_mulh, 4, v4qi, int16_t, int8_t, 8)
+DEF_COND_MULH (cond_mulh, 8, v8qi, int16_t, int8_t, 8)
+DEF_COND_MULH (cond_mulh, 16, v16qi, int16_t, int8_t, 8)
+DEF_COND_MULH (cond_mulh, 32, v32qi, int16_t, int8_t, 8)
+DEF_COND_MULH (cond_mulh, 64, v64qi, int16_t, int8_t, 8)
+DEF_COND_MULH (cond_mulh, 128, v128qi, int16_t, int8_t, 8)
+DEF_COND_MULH (cond_mulh, 256, v256qi, int16_t, int8_t, 8)
+DEF_COND_MULH (cond_mulh, 512, v512qi, int16_t, int8_t, 8)
+DEF_COND_MULH (cond_mulh, 1024, v1024qi, int16_t, int8_t, 8)
+DEF_COND_MULH (cond_mulh, 2048, v2048qi, int16_t, int8_t, 8)
+
+DEF_COND_MULH (cond_mulh, 4, v4hi, int32_t, int16_t, 16)
+DEF_COND_MULH (cond_mulh, 8, v8hi, int32_t, int16_t, 16)
+DEF_COND_MULH (cond_mulh, 16, v16hi, int32_t, int16_t, 16)
+DEF_COND_MULH (cond_mulh, 32, v32hi, int32_t, int16_t, 16)
+DEF_COND_MULH (cond_mulh, 64, v64hi, int32_t, int16_t, 16)
+DEF_COND_MULH (cond_mulh, 128, v128hi, int32_t, int16_t, 16)
+DEF_COND_MULH (cond_mulh, 256, v256hi, int32_t, int16_t, 16)
+DEF_COND_MULH (cond_mulh, 512, v512hi, int32_t, int16_t, 16)
+DEF_COND_MULH (cond_mulh, 1024, v1024hi, int32_t, int16_t, 16)
+
+DEF_COND_MULH (cond_mulh, 4, v4si, int64_t, int32_t, 32)
+DEF_COND_MULH (cond_mulh, 8, v8si, int64_t, int32_t, 32)
+DEF_COND_MULH (cond_mulh, 16, v16si, int64_t, int32_t, 32)
+DEF_COND_MULH (cond_mulh, 32, v32si, int64_t, int32_t, 32)
+DEF_COND_MULH (cond_mulh, 64, v64si, int64_t, int32_t, 32)
+DEF_COND_MULH (cond_mulh, 128, v128si, int64_t, int32_t, 32)
+DEF_COND_MULH (cond_mulh, 256, v256si, int64_t, int32_t, 32)
+DEF_COND_MULH (cond_mulh, 512, v512si, int64_t, int32_t, 32)
+
+DEF_COND_MULH (cond_mulh, 4, v4uqi, uint16_t, uint8_t, 8)
+DEF_COND_MULH (cond_mulh, 8, v8uqi, uint16_t, uint8_t, 8)
+DEF_COND_MULH (cond_mulh, 16, v16uqi, uint16_t, uint8_t, 8)
+DEF_COND_MULH (cond_mulh, 32, v32uqi, uint16_t, uint8_t, 8)
+DEF_COND_MULH (cond_mulh, 64, v64uqi, uint16_t, uint8_t, 8)
+DEF_COND_MULH (cond_mulh, 128, v128uqi, uint16_t, uint8_t, 8)
+DEF_COND_MULH (cond_mulh, 256, v256uqi, uint16_t, uint8_t, 8)
+DEF_COND_MULH (cond_mulh, 512, v512uqi, uint16_t, uint8_t, 8)
+DEF_COND_MULH (cond_mulh, 1024, v1024uqi, uint16_t, uint8_t, 8)
+DEF_COND_MULH (cond_mulh, 2048, v2048uqi, uint16_t, uint8_t, 8)
+
+DEF_COND_MULH (cond_mulh, 4, v4uhi, uint32_t, uint16_t, 16)
+DEF_COND_MULH (cond_mulh, 8, v8uhi, uint32_t, uint16_t, 16)
+DEF_COND_MULH (cond_mulh, 16, v16uhi, uint32_t, uint16_t, 16)
+DEF_COND_MULH (cond_mulh, 32, v32uhi, uint32_t, uint16_t, 16)
+DEF_COND_MULH (cond_mulh, 64, v64uhi, uint32_t, uint16_t, 16)
+DEF_COND_MULH (cond_mulh, 128, v128uhi, uint32_t, uint16_t, 16)
+DEF_COND_MULH (cond_mulh, 256, v256uhi, uint32_t, uint16_t, 16)
+DEF_COND_MULH (cond_mulh, 512, v512uhi, uint32_t, uint16_t, 16)
+DEF_COND_MULH (cond_mulh, 1024, v1024uhi, uint32_t, uint16_t, 16)
+
+DEF_COND_MULH (cond_mulh, 4, v4usi, uint64_t, uint32_t, 32)
+DEF_COND_MULH (cond_mulh, 8, v8usi, uint64_t, uint32_t, 32)
+DEF_COND_MULH (cond_mulh, 16, v16usi, uint64_t, uint32_t, 32)
+DEF_COND_MULH (cond_mulh, 32, v32usi, uint64_t, uint32_t, 32)
+DEF_COND_MULH (cond_mulh, 64, v64usi, uint64_t, uint32_t, 32)
+DEF_COND_MULH (cond_mulh, 128, v128usi, uint64_t, uint32_t, 32)
+DEF_COND_MULH (cond_mulh, 256, v256usi, uint64_t, uint32_t, 32)
+DEF_COND_MULH (cond_mulh, 512, v512usi, uint64_t, uint32_t, 32)
+
+/* { dg-final { scan-assembler-times {vmulhu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c
new file mode 100644
index 00000000000..08f2285083c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 4)
+DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 8)
+DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 16)
+DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 32)
+DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 64)
+DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 128)
+DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 256)
+DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 512)
+DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 1024)
+
+DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 4)
+DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 8)
+DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 16)
+DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 32)
+DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 64)
+DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 128)
+DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 256)
+DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 512)
+DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 1024)
+
+DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 4)
+DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 8)
+DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 16)
+DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 32)
+DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 64)
+DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 128)
+DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 256)
+DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 512)
+DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 1024)
+
+DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 4)
+DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 8)
+DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 16)
+DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 32)
+DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 64)
+DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 128)
+DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 256)
+DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 512)
+DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 1024)
+
+/* { dg-final { scan-assembler-times {vnsra\.wi\s+v[0-9]+,\s*v[0-9]+,\s*7,\s*v0.t} 18 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,\s*7,\s*v0.t} 18 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c
new file mode 100644
index 00000000000..41452e73f50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 4)
+DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 8)
+DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 16)
+DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 32)
+DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 64)
+DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 128)
+DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 256)
+DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 512)
+DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 1024)
+
+DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 4)
+DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 8)
+DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 16)
+DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 32)
+DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 64)
+DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 128)
+DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 256)
+DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 512)
+DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 1024)
+
+/* { dg-final { scan-assembler-times {vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 9 } } */
+/* { dg-final { scan-assembler-times {vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
new file mode 100644
index 00000000000..f548856ac23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
@@ -0,0 +1,72 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CONVERT (trunc, v4hi, v4qi, 4)
+DEF_COND_CONVERT (trunc, v16hi, v16qi, 16)
+DEF_COND_CONVERT (trunc, v32hi, v32qi, 32)
+DEF_COND_CONVERT (trunc, v64hi, v64qi, 64)
+DEF_COND_CONVERT (trunc, v128hi, v128qi, 128)
+DEF_COND_CONVERT (trunc, v256hi, v256qi, 256)
+DEF_COND_CONVERT (trunc, v512hi, v512qi, 512)
+DEF_COND_CONVERT (trunc, v1024hi, v1024qi, 1024)
+
+DEF_COND_CONVERT (trunc, v4si, v4hi, 4)
+DEF_COND_CONVERT (trunc, v16si, v16hi, 16)
+DEF_COND_CONVERT (trunc, v32si, v32hi, 32)
+DEF_COND_CONVERT (trunc, v64si, v64hi, 64)
+DEF_COND_CONVERT (trunc, v128si, v128hi, 128)
+DEF_COND_CONVERT (trunc, v256si, v256hi, 256)
+DEF_COND_CONVERT (trunc, v512si, v512hi, 512)
+DEF_COND_CONVERT (trunc, v1024si, v1024hi, 1024)
+
+DEF_COND_CONVERT (trunc, v4di, v4si, 4)
+DEF_COND_CONVERT (trunc, v16di, v16si, 16)
+DEF_COND_CONVERT (trunc, v32di, v32si, 32)
+DEF_COND_CONVERT (trunc, v64di, v64si, 64)
+DEF_COND_CONVERT (trunc, v128di, v128si, 128)
+DEF_COND_CONVERT (trunc, v256di, v256si, 256)
+DEF_COND_CONVERT (trunc, v512di, v512si, 512)
+
+DEF_COND_CONVERT (trunc, v4uhi, v4uqi, 4)
+DEF_COND_CONVERT (trunc, v16uhi, v16uqi, 16)
+DEF_COND_CONVERT (trunc, v32uhi, v32uqi, 32)
+DEF_COND_CONVERT (trunc, v64uhi, v64uqi, 64)
+DEF_COND_CONVERT (trunc, v128uhi, v128uqi,128)
+DEF_COND_CONVERT (trunc, v256uhi, v256uqi,256)
+DEF_COND_CONVERT (trunc, v512uhi, v512uqi,512)
+DEF_COND_CONVERT (trunc, v1024uhi, v1024uqi, 1024)
+
+DEF_COND_CONVERT (trunc, v4usi, v4uhi, 4)
+DEF_COND_CONVERT (trunc, v16usi, v16uhi, 16)
+DEF_COND_CONVERT (trunc, v32usi, v32uhi, 32)
+DEF_COND_CONVERT (trunc, v64usi, v64uhi, 64)
+DEF_COND_CONVERT (trunc, v128usi, v128uhi, 128)
+DEF_COND_CONVERT (trunc, v256usi, v256uhi, 256)
+DEF_COND_CONVERT (trunc, v512usi, v512uhi, 512)
+DEF_COND_CONVERT (trunc, v1024usi, v1024uhi, 1024)
+
+DEF_COND_CONVERT (trunc, v4udi, v4usi, 4)
+DEF_COND_CONVERT (trunc, v16udi, v16usi, 16)
+DEF_COND_CONVERT (trunc, v32udi, v32usi, 32)
+DEF_COND_CONVERT (trunc, v64udi, v64usi, 64)
+DEF_COND_CONVERT (trunc, v128udi, v128usi, 128)
+DEF_COND_CONVERT (trunc, v256udi, v256usi, 256)
+DEF_COND_CONVERT (trunc, v512udi, v512usi, 512)
+
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 46 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
new file mode 100644
index 00000000000..5d38c77bceb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CONVERT (trunc, v4si, v4qi, 4)
+DEF_COND_CONVERT (trunc, v16si, v16qi, 16)
+DEF_COND_CONVERT (trunc, v32si, v32qi, 32)
+DEF_COND_CONVERT (trunc, v64si, v64qi, 64)
+DEF_COND_CONVERT (trunc, v128si, v128qi, 128)
+DEF_COND_CONVERT (trunc, v256si, v256qi, 256)
+DEF_COND_CONVERT (trunc, v512si, v512qi, 512)
+DEF_COND_CONVERT (trunc, v1024si, v1024qi, 1024)
+
+DEF_COND_CONVERT (trunc, v4di, v4hi, 4)
+DEF_COND_CONVERT (trunc, v16di, v16hi, 16)
+DEF_COND_CONVERT (trunc, v32di, v32hi, 32)
+DEF_COND_CONVERT (trunc, v64di, v64hi, 64)
+DEF_COND_CONVERT (trunc, v128di, v128hi, 128)
+DEF_COND_CONVERT (trunc, v256di, v256hi, 256)
+DEF_COND_CONVERT (trunc, v512di, v512hi, 512)
+
+DEF_COND_CONVERT (trunc, v4usi, v4uqi, 4)
+DEF_COND_CONVERT (trunc, v16usi, v16uqi, 16)
+DEF_COND_CONVERT (trunc, v32usi, v32uqi, 32)
+DEF_COND_CONVERT (trunc, v64usi, v64uqi, 64)
+DEF_COND_CONVERT (trunc, v128usi, v128uqi, 128)
+DEF_COND_CONVERT (trunc, v256usi, v256uqi, 256)
+DEF_COND_CONVERT (trunc, v512usi, v512uqi, 512)
+DEF_COND_CONVERT (trunc, v1024usi, v1024uqi, 1024)
+
+DEF_COND_CONVERT (trunc, v4udi, v4uhi, 4)
+DEF_COND_CONVERT (trunc, v16udi, v16uhi, 16)
+DEF_COND_CONVERT (trunc, v32udi, v32uhi, 32)
+DEF_COND_CONVERT (trunc, v64udi, v64uhi, 64)
+DEF_COND_CONVERT (trunc, v128udi, v128uhi, 128)
+DEF_COND_CONVERT (trunc, v256udi, v256uhi, 256)
+DEF_COND_CONVERT (trunc, v512udi, v512uhi, 512)
+
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
new file mode 100644
index 00000000000..75967331f64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CONVERT (trunc, v4di, v4qi, 4)
+DEF_COND_CONVERT (trunc, v16di, v16qi, 16)
+DEF_COND_CONVERT (trunc, v32di, v32qi, 32)
+DEF_COND_CONVERT (trunc, v64di, v64qi, 64)
+DEF_COND_CONVERT (trunc, v128di, v128qi, 128)
+DEF_COND_CONVERT (trunc, v256di, v256qi, 256)
+DEF_COND_CONVERT (trunc, v512di, v512qi, 512)
+
+DEF_COND_CONVERT (trunc, v4udi, v4uqi, 4)
+DEF_COND_CONVERT (trunc, v16udi, v16uqi, 16)
+DEF_COND_CONVERT (trunc, v32udi, v32uqi, 32)
+DEF_COND_CONVERT (trunc, v64udi, v64uqi, 64)
+DEF_COND_CONVERT (trunc, v128udi, v128uqi, 128)
+DEF_COND_CONVERT (trunc, v256udi, v256uqi, 256)
+DEF_COND_CONVERT (trunc, v512udi, v512uqi, 512)
+
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c
new file mode 100644
index 00000000000..867de132204
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CONVERT (trunc, v4sf, v4hf, 4)
+DEF_COND_CONVERT (trunc, v16sf, v16hf, 16)
+DEF_COND_CONVERT (trunc, v32sf, v32hf, 32)
+DEF_COND_CONVERT (trunc, v64sf, v64hf, 64)
+DEF_COND_CONVERT (trunc, v128sf, v128hf, 128)
+DEF_COND_CONVERT (trunc, v256sf, v256hf, 256)
+DEF_COND_CONVERT (trunc, v512sf, v512hf, 512)
+DEF_COND_CONVERT (trunc, v1024sf, v1024hf, 1024)
+
+DEF_COND_CONVERT (trunc, v4df, v4sf, 4)
+DEF_COND_CONVERT (trunc, v16df, v16sf, 16)
+DEF_COND_CONVERT (trunc, v32df, v32sf, 32)
+DEF_COND_CONVERT (trunc, v64df, v64sf, 64)
+DEF_COND_CONVERT (trunc, v128df, v128sf, 128)
+DEF_COND_CONVERT (trunc, v256df, v256sf, 256)
+DEF_COND_CONVERT (trunc, v512df, v512sf, 512)
+
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 15 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c
new file mode 100644
index 00000000000..12ca119b8fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_CONVERT (trunc, v4df, v4hf, 4)
+DEF_COND_CONVERT (trunc, v16df, v16hf, 16)
+DEF_COND_CONVERT (trunc, v32df, v32hf, 32)
+DEF_COND_CONVERT (trunc, v64df, v64hf, 64)
+DEF_COND_CONVERT (trunc, v128df, v128hf, 128)
+DEF_COND_CONVERT (trunc, v256df, v256hf, 256)
+DEF_COND_CONVERT (trunc, v512df, v512hf, 512)
+
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 7 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c
new file mode 100644
index 00000000000..ccaaf3192c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WVV (cond_wadd, 4, qi, hi, int16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 8, qi, hi, int16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 16, qi, hi, int16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 32, qi, hi, int16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 64, qi, hi, int16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 128, qi, hi, int16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 256, qi, hi, int16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 512, qi, hi, int16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 1024, qi, hi, int16_t, +)
+
+DEF_COND_OP_WVV (cond_wadd, 4, hi, si, int32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 8, hi, si, int32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 16, hi, si, int32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 32, hi, si, int32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 64, hi, si, int32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 128, hi, si, int32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 256, hi, si, int32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 512, hi, si, int32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 1024, hi, si, int32_t, +)
+
+DEF_COND_OP_WVV (cond_wadd, 4, si, di, int64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 8, si, di, int64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 16, si, di, int64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 32, si, di, int64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 64, si, di, int64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 128, si, di, int64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 256, si, di, int64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 512, si, di, int64_t, +)
+
+DEF_COND_OP_WVV (cond_wadd, 4, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 8, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 16, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 32, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 64, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 128, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 256, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 512, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WVV (cond_wadd, 1024, uqi, uhi, uint16_t, +)
+
+DEF_COND_OP_WVV (cond_wadd, 4, uhi, usi, uint32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 8, uhi, usi, uint32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 16, uhi, usi, uint32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 32, uhi, usi, uint32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 64, uhi, usi, uint32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 128, uhi, usi, uint32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 256, uhi, usi, uint32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 512, uhi, usi, uint32_t, +)
+DEF_COND_OP_WVV (cond_wadd, 1024, uhi, usi, uint32_t, +)
+
+DEF_COND_OP_WVV (cond_wadd, 4, usi, udi, uint64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 8, usi, udi, uint64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 16, usi, udi, uint64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 32, usi, udi, uint64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 64, usi, udi, uint64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 128, usi, udi, uint64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 256, usi, udi, uint64_t, +)
+DEF_COND_OP_WVV (cond_wadd, 512, usi, udi, uint64_t, +)
+
+/* { dg-final { scan-assembler-times {vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-times {vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c
new file mode 100644
index 00000000000..d2a67c85454
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WVV (cond_wadd, 4, hf, sf, float, +)
+DEF_COND_OP_WVV (cond_wadd, 8, hf, sf, float, +)
+DEF_COND_OP_WVV (cond_wadd, 16, hf, sf, float, +)
+DEF_COND_OP_WVV (cond_wadd, 32, hf, sf, float, +)
+DEF_COND_OP_WVV (cond_wadd, 64, hf, sf, float, +)
+DEF_COND_OP_WVV (cond_wadd, 128, hf, sf, float, +)
+DEF_COND_OP_WVV (cond_wadd, 256, hf, sf, float, +)
+DEF_COND_OP_WVV (cond_wadd, 512, hf, sf, float, +)
+DEF_COND_OP_WVV (cond_wadd, 1024, hf, sf, float, +)
+
+DEF_COND_OP_WVV (cond_wadd, 4, sf, df, double, +)
+DEF_COND_OP_WVV (cond_wadd, 8, sf, df, double, +)
+DEF_COND_OP_WVV (cond_wadd, 16, sf, df, double, +)
+DEF_COND_OP_WVV (cond_wadd, 32, sf, df, double, +)
+DEF_COND_OP_WVV (cond_wadd, 64, sf, df, double, +)
+DEF_COND_OP_WVV (cond_wadd, 128, sf, df, double, +)
+DEF_COND_OP_WVV (cond_wadd, 256, sf, df, double, +)
+DEF_COND_OP_WVV (cond_wadd, 512, sf, df, double, +)
+
+/* { dg-final { scan-assembler-times {vfwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c
new file mode 100644
index 00000000000..6ae95f30241
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WWV (cond_wadd, 4, qi, hi, int16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 8, qi, hi, int16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 16, qi, hi, int16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 32, qi, hi, int16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 64, qi, hi, int16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 128, qi, hi, int16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 256, qi, hi, int16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 512, qi, hi, int16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 1024, qi, hi, int16_t, +)
+
+DEF_COND_OP_WWV (cond_wadd, 4, hi, si, int32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 8, hi, si, int32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 16, hi, si, int32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 32, hi, si, int32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 64, hi, si, int32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 128, hi, si, int32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 256, hi, si, int32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 512, hi, si, int32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 1024, hi, si, int32_t, +)
+
+DEF_COND_OP_WWV (cond_wadd, 4, si, di, int64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 8, si, di, int64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 16, si, di, int64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 32, si, di, int64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 64, si, di, int64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 128, si, di, int64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 256, si, di, int64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 512, si, di, int64_t, +)
+
+DEF_COND_OP_WWV (cond_wadd, 4, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 8, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 16, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 32, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 64, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 128, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 256, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 512, uqi, uhi, uint16_t, +)
+DEF_COND_OP_WWV (cond_wadd, 1024, uqi, uhi, uint16_t, +)
+
+DEF_COND_OP_WWV (cond_wadd, 4, uhi, usi, uint32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 8, uhi, usi, uint32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 16, uhi, usi, uint32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 32, uhi, usi, uint32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 64, uhi, usi, uint32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 128, uhi, usi, uint32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 256, uhi, usi, uint32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 512, uhi, usi, uint32_t, +)
+DEF_COND_OP_WWV (cond_wadd, 1024, uhi, usi, uint32_t, +)
+
+DEF_COND_OP_WWV (cond_wadd, 4, usi, udi, uint64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 8, usi, udi, uint64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 16, usi, udi, uint64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 32, usi, udi, uint64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 64, usi, udi, uint64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 128, usi, udi, uint64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 256, usi, udi, uint64_t, +)
+DEF_COND_OP_WWV (cond_wadd, 512, usi, udi, uint64_t, +)
+
+/* { dg-final { scan-assembler-times {vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-times {vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c
new file mode 100644
index 00000000000..d9056e67c08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WWV (cond_wadd, 4, hf, sf, float, +)
+DEF_COND_OP_WWV (cond_wadd, 8, hf, sf, float, +)
+DEF_COND_OP_WWV (cond_wadd, 16, hf, sf, float, +)
+DEF_COND_OP_WWV (cond_wadd, 32, hf, sf, float, +)
+DEF_COND_OP_WWV (cond_wadd, 64, hf, sf, float, +)
+DEF_COND_OP_WWV (cond_wadd, 128, hf, sf, float, +)
+DEF_COND_OP_WWV (cond_wadd, 256, hf, sf, float, +)
+DEF_COND_OP_WWV (cond_wadd, 512, hf, sf, float, +)
+DEF_COND_OP_WWV (cond_wadd, 1024, hf, sf, float, +)
+
+DEF_COND_OP_WWV (cond_wadd, 4, sf, df, double, +)
+DEF_COND_OP_WWV (cond_wadd, 8, sf, df, double, +)
+DEF_COND_OP_WWV (cond_wadd, 16, sf, df, double, +)
+DEF_COND_OP_WWV (cond_wadd, 32, sf, df, double, +)
+DEF_COND_OP_WWV (cond_wadd, 64, sf, df, double, +)
+DEF_COND_OP_WWV (cond_wadd, 128, sf, df, double, +)
+DEF_COND_OP_WWV (cond_wadd, 256, sf, df, double, +)
+DEF_COND_OP_WWV (cond_wadd, 512, sf, df, double, +)
+
+/* { dg-final { scan-assembler-times {vfwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c
new file mode 100644
index 00000000000..fa4022bcc7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_WFMA_VV (cond_wfma, 4, qi, hi, int16_t)
+DEF_WFMA_VV (cond_wfma, 8, qi, hi, int16_t)
+DEF_WFMA_VV (cond_wfma, 16, qi, hi, int16_t)
+DEF_WFMA_VV (cond_wfma, 32, qi, hi, int16_t)
+DEF_WFMA_VV (cond_wfma, 64, qi, hi, int16_t)
+DEF_WFMA_VV (cond_wfma, 128, qi, hi, int16_t)
+DEF_WFMA_VV (cond_wfma, 256, qi, hi, int16_t)
+DEF_WFMA_VV (cond_wfma, 512, qi, hi, int16_t)
+DEF_WFMA_VV (cond_wfma, 1024, qi, hi, int16_t)
+
+DEF_WFMA_VV (cond_wfma, 4, hi, si, int32_t)
+DEF_WFMA_VV (cond_wfma, 8, hi, si, int32_t)
+DEF_WFMA_VV (cond_wfma, 16, hi, si, int32_t)
+DEF_WFMA_VV (cond_wfma, 32, hi, si, int32_t)
+DEF_WFMA_VV (cond_wfma, 64, hi, si, int32_t)
+DEF_WFMA_VV (cond_wfma, 128, hi, si, int32_t)
+DEF_WFMA_VV (cond_wfma, 256, hi, si, int32_t)
+DEF_WFMA_VV (cond_wfma, 512, hi, si, int32_t)
+DEF_WFMA_VV (cond_wfma, 1024, hi, si, int32_t)
+
+DEF_WFMA_VV (cond_wfma, 4, si, di, int64_t)
+DEF_WFMA_VV (cond_wfma, 8, si, di, int64_t)
+DEF_WFMA_VV (cond_wfma, 16, si, di, int64_t)
+DEF_WFMA_VV (cond_wfma, 32, si, di, int64_t)
+DEF_WFMA_VV (cond_wfma, 64, si, di, int64_t)
+DEF_WFMA_VV (cond_wfma, 128, si, di, int64_t)
+DEF_WFMA_VV (cond_wfma, 256, si, di, int64_t)
+DEF_WFMA_VV (cond_wfma, 512, si, di, int64_t)
+
+DEF_WFMA_VV (cond_wfma, 4, uqi, uhi, uint16_t)
+DEF_WFMA_VV (cond_wfma, 8, uqi, uhi, uint16_t)
+DEF_WFMA_VV (cond_wfma, 16, uqi, uhi, uint16_t)
+DEF_WFMA_VV (cond_wfma, 32, uqi, uhi, uint16_t)
+DEF_WFMA_VV (cond_wfma, 64, uqi, uhi, uint16_t)
+DEF_WFMA_VV (cond_wfma, 128, uqi, uhi, uint16_t)
+DEF_WFMA_VV (cond_wfma, 256, uqi, uhi, uint16_t)
+DEF_WFMA_VV (cond_wfma, 512, uqi, uhi, uint16_t)
+DEF_WFMA_VV (cond_wfma, 1024, uqi, uhi, uint16_t)
+
+DEF_WFMA_VV (cond_wfma, 4, uhi, usi, uint32_t)
+DEF_WFMA_VV (cond_wfma, 8, uhi, usi, uint32_t)
+DEF_WFMA_VV (cond_wfma, 16, uhi, usi, uint32_t)
+DEF_WFMA_VV (cond_wfma, 32, uhi, usi, uint32_t)
+DEF_WFMA_VV (cond_wfma, 64, uhi, usi, uint32_t)
+DEF_WFMA_VV (cond_wfma, 128, uhi, usi, uint32_t)
+DEF_WFMA_VV (cond_wfma, 256, uhi, usi, uint32_t)
+DEF_WFMA_VV (cond_wfma, 512, uhi, usi, uint32_t)
+DEF_WFMA_VV (cond_wfma, 1024, uhi, usi, uint32_t)
+
+DEF_WFMA_VV (cond_wfma, 4, usi, udi, uint64_t)
+DEF_WFMA_VV (cond_wfma, 8, usi, udi, uint64_t)
+DEF_WFMA_VV (cond_wfma, 16, usi, udi, uint64_t)
+DEF_WFMA_VV (cond_wfma, 32, usi, udi, uint64_t)
+DEF_WFMA_VV (cond_wfma, 64, usi, udi, uint64_t)
+DEF_WFMA_VV (cond_wfma, 128, usi, udi, uint64_t)
+DEF_WFMA_VV (cond_wfma, 256, usi, udi, uint64_t)
+DEF_WFMA_VV (cond_wfma, 512, usi, udi, uint64_t)
+
+/* { dg-final { scan-assembler-times {vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-times {vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c
new file mode 100644
index 00000000000..5a2bfed9bc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_WFMA_VV (cond_wfma, 4, hf, sf, float)
+DEF_WFMA_VV (cond_wfma, 8, hf, sf, float)
+DEF_WFMA_VV (cond_wfma, 16, hf, sf, float)
+DEF_WFMA_VV (cond_wfma, 32, hf, sf, float)
+DEF_WFMA_VV (cond_wfma, 64, hf, sf, float)
+DEF_WFMA_VV (cond_wfma, 128, hf, sf, float)
+DEF_WFMA_VV (cond_wfma, 256, hf, sf, float)
+DEF_WFMA_VV (cond_wfma, 512, hf, sf, float)
+DEF_WFMA_VV (cond_wfma, 1024, hf, sf, float)
+
+DEF_WFMA_VV (cond_wfma, 4, sf, df, double)
+DEF_WFMA_VV (cond_wfma, 8, sf, df, double)
+DEF_WFMA_VV (cond_wfma, 16, sf, df, double)
+DEF_WFMA_VV (cond_wfma, 32, sf, df, double)
+DEF_WFMA_VV (cond_wfma, 64, sf, df, double)
+DEF_WFMA_VV (cond_wfma, 128, sf, df, double)
+DEF_WFMA_VV (cond_wfma, 256, sf, df, double)
+DEF_WFMA_VV (cond_wfma, 512, sf, df, double)
+
+/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c
new file mode 100644
index 00000000000..86fbe0bde73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_WFMS_VV (cond_wfms, 4, hf, sf, float)
+DEF_WFMS_VV (cond_wfms, 8, hf, sf, float)
+DEF_WFMS_VV (cond_wfms, 16, hf, sf, float)
+DEF_WFMS_VV (cond_wfms, 32, hf, sf, float)
+DEF_WFMS_VV (cond_wfms, 64, hf, sf, float)
+DEF_WFMS_VV (cond_wfms, 128, hf, sf, float)
+DEF_WFMS_VV (cond_wfms, 256, hf, sf, float)
+DEF_WFMS_VV (cond_wfms, 512, hf, sf, float)
+DEF_WFMS_VV (cond_wfms, 1024, hf, sf, float)
+
+DEF_WFMS_VV (cond_wfms, 4, sf, df, double)
+DEF_WFMS_VV (cond_wfms, 8, sf, df, double)
+DEF_WFMS_VV (cond_wfms, 16, sf, df, double)
+DEF_WFMS_VV (cond_wfms, 32, sf, df, double)
+DEF_WFMS_VV (cond_wfms, 64, sf, df, double)
+DEF_WFMS_VV (cond_wfms, 128, sf, df, double)
+DEF_WFMS_VV (cond_wfms, 256, sf, df, double)
+DEF_WFMS_VV (cond_wfms, 512, sf, df, double)
+
+/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c
new file mode 100644
index 00000000000..fa0fc64367d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_WFNMA_VV (cond_wfnma, 4, hf, sf, float)
+DEF_WFNMA_VV (cond_wfnma, 8, hf, sf, float)
+DEF_WFNMA_VV (cond_wfnma, 16, hf, sf, float)
+DEF_WFNMA_VV (cond_wfnma, 32, hf, sf, float)
+DEF_WFNMA_VV (cond_wfnma, 64, hf, sf, float)
+DEF_WFNMA_VV (cond_wfnma, 128, hf, sf, float)
+DEF_WFNMA_VV (cond_wfnma, 256, hf, sf, float)
+DEF_WFNMA_VV (cond_wfnma, 512, hf, sf, float)
+DEF_WFNMA_VV (cond_wfnma, 1024, hf, sf, float)
+
+DEF_WFNMA_VV (cond_wfnma, 4, sf, df, double)
+DEF_WFNMA_VV (cond_wfnma, 8, sf, df, double)
+DEF_WFNMA_VV (cond_wfnma, 16, sf, df, double)
+DEF_WFNMA_VV (cond_wfnma, 32, sf, df, double)
+DEF_WFNMA_VV (cond_wfnma, 64, sf, df, double)
+DEF_WFNMA_VV (cond_wfnma, 128, sf, df, double)
+DEF_WFNMA_VV (cond_wfnma, 256, sf, df, double)
+DEF_WFNMA_VV (cond_wfnma, 512, sf, df, double)
+
+/* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c
new file mode 100644
index 00000000000..f18cd66489d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WVV (cond_wmul, 4, qi, hi, int16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 8, qi, hi, int16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 16, qi, hi, int16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 32, qi, hi, int16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 64, qi, hi, int16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 128, qi, hi, int16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 256, qi, hi, int16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 512, qi, hi, int16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 1024, qi, hi, int16_t, *)
+
+DEF_COND_OP_WVV (cond_wmul, 4, hi, si, int32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 8, hi, si, int32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 16, hi, si, int32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 32, hi, si, int32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 64, hi, si, int32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 128, hi, si, int32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 256, hi, si, int32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 512, hi, si, int32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 1024, hi, si, int32_t, *)
+
+DEF_COND_OP_WVV (cond_wmul, 4, si, di, int64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 8, si, di, int64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 16, si, di, int64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 32, si, di, int64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 64, si, di, int64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 128, si, di, int64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 256, si, di, int64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 512, si, di, int64_t, *)
+
+DEF_COND_OP_WVV (cond_wmul, 4, uqi, uhi, uint16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 8, uqi, uhi, uint16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 16, uqi, uhi, uint16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 32, uqi, uhi, uint16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 64, uqi, uhi, uint16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 128, uqi, uhi, uint16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 256, uqi, uhi, uint16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 512, uqi, uhi, uint16_t, *)
+DEF_COND_OP_WVV (cond_wmul, 1024, uqi, uhi, uint16_t, *)
+
+DEF_COND_OP_WVV (cond_wmul, 4, uhi, usi, uint32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 8, uhi, usi, uint32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 16, uhi, usi, uint32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 32, uhi, usi, uint32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 64, uhi, usi, uint32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 128, uhi, usi, uint32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 256, uhi, usi, uint32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 512, uhi, usi, uint32_t, *)
+DEF_COND_OP_WVV (cond_wmul, 1024, uhi, usi, uint32_t, *)
+
+DEF_COND_OP_WVV (cond_wmul, 4, usi, udi, uint64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 8, usi, udi, uint64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 16, usi, udi, uint64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 32, usi, udi, uint64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 64, usi, udi, uint64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 128, usi, udi, uint64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 256, usi, udi, uint64_t, *)
+DEF_COND_OP_WVV (cond_wmul, 512, usi, udi, uint64_t, *)
+
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c
new file mode 100644
index 00000000000..b7a6d52931f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WVV (cond_wmul, 4, hf, sf, float, *)
+DEF_COND_OP_WVV (cond_wmul, 8, hf, sf, float, *)
+DEF_COND_OP_WVV (cond_wmul, 16, hf, sf, float, *)
+DEF_COND_OP_WVV (cond_wmul, 32, hf, sf, float, *)
+DEF_COND_OP_WVV (cond_wmul, 64, hf, sf, float, *)
+DEF_COND_OP_WVV (cond_wmul, 128, hf, sf, float, *)
+DEF_COND_OP_WVV (cond_wmul, 256, hf, sf, float, *)
+DEF_COND_OP_WVV (cond_wmul, 512, hf, sf, float, *)
+DEF_COND_OP_WVV (cond_wmul, 1024, hf, sf, float, *)
+
+DEF_COND_OP_WVV (cond_wmul, 4, sf, df, double, *)
+DEF_COND_OP_WVV (cond_wmul, 8, sf, df, double, *)
+DEF_COND_OP_WVV (cond_wmul, 16, sf, df, double, *)
+DEF_COND_OP_WVV (cond_wmul, 32, sf, df, double, *)
+DEF_COND_OP_WVV (cond_wmul, 64, sf, df, double, *)
+DEF_COND_OP_WVV (cond_wmul, 128, sf, df, double, *)
+DEF_COND_OP_WVV (cond_wmul, 256, sf, df, double, *)
+DEF_COND_OP_WVV (cond_wmul, 512, sf, df, double, *)
+
+/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c
new file mode 100644
index 00000000000..64ca747f649
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WVV_SU (cond_wmul, 4, qi, hi, int16_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 8, qi, hi, int16_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 16, qi, hi, int16_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 32, qi, hi, int16_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 64, qi, hi, int16_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 128, qi, hi, int16_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 256, qi, hi, int16_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 512, qi, hi, int16_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 1024, qi, hi, int16_t, *)
+
+DEF_COND_OP_WVV_SU (cond_wmul, 4, hi, si, int32_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 8, hi, si, int32_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 16, hi, si, int32_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 32, hi, si, int32_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 64, hi, si, int32_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 128, hi, si, int32_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 256, hi, si, int32_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 512, hi, si, int32_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 1024, hi, si, int32_t, *)
+
+DEF_COND_OP_WVV_SU (cond_wmul, 4, si, di, int64_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 8, si, di, int64_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 16, si, di, int64_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 32, si, di, int64_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 64, si, di, int64_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 128, si, di, int64_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 256, si, di, int64_t, *)
+DEF_COND_OP_WVV_SU (cond_wmul, 512, si, di, int64_t, *)
+
+/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c
new file mode 100644
index 00000000000..887aabd5c19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WVV (cond_wsub, 4, qi, hi, int16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 8, qi, hi, int16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 16, qi, hi, int16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 32, qi, hi, int16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 64, qi, hi, int16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 128, qi, hi, int16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 256, qi, hi, int16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 512, qi, hi, int16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 1024, qi, hi, int16_t, -)
+
+DEF_COND_OP_WVV (cond_wsub, 4, hi, si, int32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 8, hi, si, int32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 16, hi, si, int32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 32, hi, si, int32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 64, hi, si, int32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 128, hi, si, int32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 256, hi, si, int32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 512, hi, si, int32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 1024, hi, si, int32_t, -)
+
+DEF_COND_OP_WVV (cond_wsub, 4, si, di, int64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 8, si, di, int64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 16, si, di, int64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 32, si, di, int64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 64, si, di, int64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 128, si, di, int64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 256, si, di, int64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 512, si, di, int64_t, -)
+
+DEF_COND_OP_WVV (cond_wsub, 4, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 8, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 16, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 32, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 64, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 128, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 256, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 512, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WVV (cond_wsub, 1024, uqi, uhi, uint16_t, -)
+
+DEF_COND_OP_WVV (cond_wsub, 4, uhi, usi, uint32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 8, uhi, usi, uint32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 16, uhi, usi, uint32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 32, uhi, usi, uint32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 64, uhi, usi, uint32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 128, uhi, usi, uint32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 256, uhi, usi, uint32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 512, uhi, usi, uint32_t, -)
+DEF_COND_OP_WVV (cond_wsub, 1024, uhi, usi, uint32_t, -)
+
+DEF_COND_OP_WVV (cond_wsub, 4, usi, udi, uint64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 8, usi, udi, uint64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 16, usi, udi, uint64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 32, usi, udi, uint64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 64, usi, udi, uint64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 128, usi, udi, uint64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 256, usi, udi, uint64_t, -)
+DEF_COND_OP_WVV (cond_wsub, 512, usi, udi, uint64_t, -)
+
+/* { dg-final { scan-assembler-times {vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c
new file mode 100644
index 00000000000..4093450374e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WVV (cond_wsub, 4, hf, sf, float, -)
+DEF_COND_OP_WVV (cond_wsub, 8, hf, sf, float, -)
+DEF_COND_OP_WVV (cond_wsub, 16, hf, sf, float, -)
+DEF_COND_OP_WVV (cond_wsub, 32, hf, sf, float, -)
+DEF_COND_OP_WVV (cond_wsub, 64, hf, sf, float, -)
+DEF_COND_OP_WVV (cond_wsub, 128, hf, sf, float, -)
+DEF_COND_OP_WVV (cond_wsub, 256, hf, sf, float, -)
+DEF_COND_OP_WVV (cond_wsub, 512, hf, sf, float, -)
+DEF_COND_OP_WVV (cond_wsub, 1024, hf, sf, float, -)
+
+DEF_COND_OP_WVV (cond_wsub, 4, sf, df, double, -)
+DEF_COND_OP_WVV (cond_wsub, 8, sf, df, double, -)
+DEF_COND_OP_WVV (cond_wsub, 16, sf, df, double, -)
+DEF_COND_OP_WVV (cond_wsub, 32, sf, df, double, -)
+DEF_COND_OP_WVV (cond_wsub, 64, sf, df, double, -)
+DEF_COND_OP_WVV (cond_wsub, 128, sf, df, double, -)
+DEF_COND_OP_WVV (cond_wsub, 256, sf, df, double, -)
+DEF_COND_OP_WVV (cond_wsub, 512, sf, df, double, -)
+
+/* { dg-final { scan-assembler-times {vfwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c
new file mode 100644
index 00000000000..20e3a8fb05a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WWV (cond_wsub, 4, qi, hi, int16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 8, qi, hi, int16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 16, qi, hi, int16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 32, qi, hi, int16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 64, qi, hi, int16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 128, qi, hi, int16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 256, qi, hi, int16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 512, qi, hi, int16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 1024, qi, hi, int16_t, -)
+
+DEF_COND_OP_WWV (cond_wsub, 4, hi, si, int32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 8, hi, si, int32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 16, hi, si, int32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 32, hi, si, int32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 64, hi, si, int32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 128, hi, si, int32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 256, hi, si, int32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 512, hi, si, int32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 1024, hi, si, int32_t, -)
+
+DEF_COND_OP_WWV (cond_wsub, 4, si, di, int64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 8, si, di, int64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 16, si, di, int64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 32, si, di, int64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 64, si, di, int64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 128, si, di, int64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 256, si, di, int64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 512, si, di, int64_t, -)
+
+DEF_COND_OP_WWV (cond_wsub, 4, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 8, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 16, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 32, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 64, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 128, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 256, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 512, uqi, uhi, uint16_t, -)
+DEF_COND_OP_WWV (cond_wsub, 1024, uqi, uhi, uint16_t, -)
+
+DEF_COND_OP_WWV (cond_wsub, 4, uhi, usi, uint32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 8, uhi, usi, uint32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 16, uhi, usi, uint32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 32, uhi, usi, uint32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 64, uhi, usi, uint32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 128, uhi, usi, uint32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 256, uhi, usi, uint32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 512, uhi, usi, uint32_t, -)
+DEF_COND_OP_WWV (cond_wsub, 1024, uhi, usi, uint32_t, -)
+
+DEF_COND_OP_WWV (cond_wsub, 4, usi, udi, uint64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 8, usi, udi, uint64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 16, usi, udi, uint64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 32, usi, udi, uint64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 64, usi, udi, uint64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 128, usi, udi, uint64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 256, usi, udi, uint64_t, -)
+DEF_COND_OP_WWV (cond_wsub, 512, usi, udi, uint64_t, -)
+
+/* { dg-final { scan-assembler-times {vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c
new file mode 100644
index 00000000000..b97cd8a0592
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_OP_WWV (cond_wsub, 4, hf, sf, float, -)
+DEF_COND_OP_WWV (cond_wsub, 8, hf, sf, float, -)
+DEF_COND_OP_WWV (cond_wsub, 16, hf, sf, float, -)
+DEF_COND_OP_WWV (cond_wsub, 32, hf, sf, float, -)
+DEF_COND_OP_WWV (cond_wsub, 64, hf, sf, float, -)
+DEF_COND_OP_WWV (cond_wsub, 128, hf, sf, float, -)
+DEF_COND_OP_WWV (cond_wsub, 256, hf, sf, float, -)
+DEF_COND_OP_WWV (cond_wsub, 512, hf, sf, float, -)
+DEF_COND_OP_WWV (cond_wsub, 1024, hf, sf, float, -)
+
+DEF_COND_OP_WWV (cond_wsub, 4, sf, df, double, -)
+DEF_COND_OP_WWV (cond_wsub, 8, sf, df, double, -)
+DEF_COND_OP_WWV (cond_wsub, 16, sf, df, double, -)
+DEF_COND_OP_WWV (cond_wsub, 32, sf, df, double, -)
+DEF_COND_OP_WWV (cond_wsub, 64, sf, df, double, -)
+DEF_COND_OP_WWV (cond_wsub, 128, sf, df, double, -)
+DEF_COND_OP_WWV (cond_wsub, 256, sf, df, double, -)
+DEF_COND_OP_WWV (cond_wsub, 512, sf, df, double, -)
+
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 87a7ab47c23..fa124ffd698 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -670,3 +670,157 @@ typedef double v512df __attribute__ ((vector_size (4096)));
for (int i = 0; i < NUM; ++i) \
a[i] = -((TYPE2) b[i] * (TYPE2) c[i]) - d[i]; \
}
+
+#define DEF_WIDEN_REDUC_PLUS(TYPE, TYPE2, NUM) \
+ TYPE2 __attribute__ ((noinline, noclone)) \
+ reduc_plus_##TYPE##_##TYPE2##NUM (TYPE *__restrict a) \
+ { \
+ TYPE2 r = 0; \
+ for (int i = 0; i < NUM; ++i) \
+ r += a[i]; \
+ return r; \
+ }
+
+#define DEF_NARROW_TRUNC_IMM(TYPE1, TYPE2, NUM) \
+ void narrow_##TYPE1##_##TYPE2##_##NUM (TYPE1 *restrict a, TYPE2 *restrict b) \
+ { \
+ for (int i = 0; i < NUM; i += 1) \
+ a[i] = (TYPE1) (b[i] >> 7); \
+ }
+
+#define DEF_NARROW_TRUNC_XREG(TYPE1, TYPE2, NUM) \
+ void narrow_##TYPE1##_##TYPE2##_##NUM (TYPE1 *restrict a, TYPE2 *restrict b, \
+ int shift) \
+ { \
+ for (int i = 0; i < NUM; i += 1) \
+ a[i] = (TYPE1) (b[i] >> shift); \
+ }
+
+#define DEF_NARROW_TRUNC_VREG(TYPE1, TYPE2, NUM) \
+ void narrow_##TYPE1##_##TYPE2##_##NUM (TYPE1 *restrict a, TYPE2 *restrict b, \
+ int *restrict shift) \
+ { \
+ for (int i = 0; i < NUM; i += 1) \
+ a[i] = (TYPE1) (b[i] >> shift[i]); \
+ }
+
+#define DEF_COND_CONVERT(PREFIX, TYPE1, TYPE2, NUM) \
+ __attribute__ ((noipa)) \
+ TYPE2 PREFIX##_##TYPE1##TYPE2##_##NUM (TYPE2 dst, TYPE1 a, int *cond) \
+ { \
+ for (int i = 0; i < NUM; i++) \
+ dst[i] = cond[i] ? a[i] : dst[i]; \
+ return dst; \
+ }
+
+#define DEF_COND_FP_CONVERT(PREFIX, TYPE1, TYPE2, TYPE3, NUM) \
+ __attribute__ ((noipa)) \
+ v##NUM##TYPE2 PREFIX##_##TYPE1##TYPE2##TYPE3##_##NUM (v##NUM##TYPE2 dst, \
+ v##NUM##TYPE1 a, \
+ int *cond) \
+ { \
+ for (int i = 0; i < NUM; i++) \
+ dst[i] = cond[i] ? (TYPE3) a[i] : dst[i]; \
+ return dst; \
+ }
+
+#define DEF_COND_CALL(PREFIX, NUM, TYPE, CALL) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \
+ { \
+ TYPE v; \
+ for (int i = 0; i < NUM; ++i) \
+ v[i] = cond[i] ? CALL (a[i], b[i]) : c[i]; \
+ return v; \
+ }
+
+#define DEF_COND_MULH(PREFIX, NUM, TYPE, TYPE2, TYPE3, SHIFT) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \
+ { \
+ TYPE v; \
+ for (int i = 0; i < NUM; ++i) \
+ v[i] \
+ = cond[i] ? (TYPE3) (((TYPE2) a[i] * (TYPE2) b[i]) >> SHIFT) : c[i]; \
+ return v; \
+ }
+
+#define DEF_COND_OP_WVV(PREFIX, NUM, TYPE, TYPE2, TYPE3, OP) \
+ v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##_##TYPE2##NUM (v##NUM##TYPE2 a, v##NUM##TYPE b, \
+ v##NUM##TYPE c, int *restrict cond) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = cond[i] ? (TYPE3) b[i] OP (TYPE3) c[i] : a[i]; \
+ return a; \
+ }
+
+#define DEF_COND_OP_WVV_SU(PREFIX, NUM, TYPE, TYPE2, TYPE3, OP) \
+ v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##_##TYPE2##NUM (v##NUM##TYPE2 a, v##NUM##u##TYPE b, \
+ v##NUM##TYPE c, int *restrict cond) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = cond[i] ? (TYPE3) b[i] OP (TYPE3) c[i] : a[i]; \
+ return a; \
+ }
+
+#define DEF_COND_OP_WWV(PREFIX, NUM, TYPE, TYPE2, TYPE3, OP) \
+ v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##_##TYPE2##NUM (v##NUM##TYPE2 a, v##NUM##TYPE2 b, \
+ v##NUM##TYPE c, int *restrict cond) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = cond[i] ? (TYPE3) b[i] OP (TYPE3) c[i] : a[i]; \
+ return a; \
+ }
+
+#define DEF_WFMA_VV(PREFIX, NUM, TYPE, TYPE2, TYPE3) \
+ v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##TYPE2##TYPE3##NUM (v##NUM##TYPE2 a, v##NUM##TYPE b, \
+ v##NUM##TYPE c, int *restrict cond) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = cond[i] ? (TYPE3) b[i] * (TYPE3) c[i] + a[i] : a[i]; \
+ return a; \
+ }
+
+#define DEF_WFNMA_VV(PREFIX, NUM, TYPE, TYPE2, TYPE3) \
+ v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##TYPE2##TYPE3##NUM (v##NUM##TYPE2 a, v##NUM##TYPE b, \
+ v##NUM##TYPE c, int *restrict cond) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = cond[i] ? a[i] - (TYPE3) b[i] * (TYPE3) c[i] : a[i]; \
+ return a; \
+ }
+
+#define DEF_WFMS_VV(PREFIX, NUM, TYPE, TYPE2, TYPE3) \
+ v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##TYPE2##TYPE3##NUM (v##NUM##TYPE2 a, v##NUM##TYPE b, \
+ v##NUM##TYPE c, int *restrict cond) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = cond[i] ? (TYPE3) b[i] * (TYPE3) c[i] - a[i] : a[i]; \
+ return a; \
+ }
+
+#define DEF_COND_NARROW_TRUNC_IMM(TYPE1, TYPE2, TYPE3, NUM) \
+ v##NUM##TYPE1 narrow_##TYPE1##_##TYPE2##_##NUM (v##NUM##TYPE1 a, \
+ v##NUM##TYPE2 b, \
+ int *__restrict cond) \
+ { \
+ for (int i = 0; i < NUM; i += 1) \
+ a[i] = cond[i] ? (TYPE3) (b[i] >> 7) : a[i]; \
+ return a; \
+ }
+
+#define DEF_COND_NARROW_TRUNC_XREG(TYPE1, TYPE2, TYPE3, NUM) \
+ v##NUM##TYPE1 narrow_##TYPE1##_##TYPE2##_##NUM (v##NUM##TYPE1 a, \
+ v##NUM##TYPE2 b, int shift, \
+ int *__restrict cond) \
+ { \
+ for (int i = 0; i < NUM; i += 1) \
+ a[i] = cond[i] ? (TYPE3) (b[i] >> shift) : a[i]; \
+ return a; \
+ }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c
new file mode 100644
index 00000000000..ca6b856aca4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 4)
+DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 8)
+DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 16)
+DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 32)
+DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 64)
+DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 128)
+DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 256)
+DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 512)
+DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 1024)
+DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 2048)
+
+DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 4)
+DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 8)
+DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 16)
+DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 32)
+DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 64)
+DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 128)
+DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 256)
+DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 512)
+DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 1024)
+
+DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 4)
+DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 8)
+DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 16)
+DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 32)
+DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 64)
+DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 128)
+DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 256)
+DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 512)
+
+/* { dg-final { scan-assembler-times {vnsra\.wi} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c
new file mode 100644
index 00000000000..3838ee5fd68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 4)
+DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 8)
+DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 16)
+DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 32)
+DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 64)
+DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 128)
+DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 256)
+DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 512)
+
+/* { dg-final { scan-assembler-times {vnsra\.wx} 8 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c
new file mode 100644
index 00000000000..03d03dc9c0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 4)
+DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 8)
+DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 16)
+DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 32)
+DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 64)
+DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 128)
+DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 256)
+DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 512)
+
+/* { dg-final { scan-assembler-times {vnsra\.wv} 8 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c
new file mode 100644
index 00000000000..7ce910cbfce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c
@@ -0,0 +1,80 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 4)
+DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 8)
+DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 16)
+DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 32)
+DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 64)
+DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 128)
+DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 256)
+DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 512)
+DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 1024)
+DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 2048)
+
+DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 4)
+DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 8)
+DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 16)
+DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 32)
+DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 64)
+DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 128)
+DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 256)
+DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 512)
+DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 1024)
+
+DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 4)
+DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 8)
+DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 16)
+DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 32)
+DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 64)
+DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 128)
+DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 256)
+DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 512)
+
+DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 4)
+DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 8)
+DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 16)
+DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 32)
+DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 64)
+DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 128)
+DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 256)
+DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 512)
+DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 1024)
+DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 2048)
+
+DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 4)
+DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 8)
+DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 16)
+DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 32)
+DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 64)
+DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 128)
+DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 256)
+DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 512)
+DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 1024)
+
+DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 4)
+DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 8)
+DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 16)
+DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 32)
+DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 64)
+DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 128)
+DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 256)
+DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 512)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs} 19 } } */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs} 19 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c
new file mode 100644
index 00000000000..75d49bc2528
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_WIDEN_REDUC_PLUS (_Float16, float, 4)
+DEF_WIDEN_REDUC_PLUS (_Float16, float, 8)
+DEF_WIDEN_REDUC_PLUS (_Float16, float, 16)
+DEF_WIDEN_REDUC_PLUS (_Float16, float, 32)
+DEF_WIDEN_REDUC_PLUS (_Float16, float, 64)
+DEF_WIDEN_REDUC_PLUS (_Float16, float, 128)
+DEF_WIDEN_REDUC_PLUS (_Float16, float, 256)
+DEF_WIDEN_REDUC_PLUS (_Float16, float, 512)
+DEF_WIDEN_REDUC_PLUS (_Float16, float, 1024)
+
+DEF_WIDEN_REDUC_PLUS (float, double, 4)
+DEF_WIDEN_REDUC_PLUS (float, double, 8)
+DEF_WIDEN_REDUC_PLUS (float, double, 16)
+DEF_WIDEN_REDUC_PLUS (float, double, 32)
+DEF_WIDEN_REDUC_PLUS (float, double, 64)
+DEF_WIDEN_REDUC_PLUS (float, double, 128)
+DEF_WIDEN_REDUC_PLUS (float, double, 256)
+DEF_WIDEN_REDUC_PLUS (float, double, 512)
+
+/* { dg-final { scan-assembler-times {vfwredusum\.vs} 17 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c
new file mode 100644
index 00000000000..f49acc14d7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "wred-2.c"
+
+/* { dg-final { scan-assembler-times {vfwredosum\.vs} 17 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
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2023-09-26 15:13 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Support full coverage VLS combine support Jeff Law
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