[gcc r14-4340] RISC-V: Replace not + bitwise_imm with li + bitwise_not

[gcc r14-4340] RISC-V: Replace not + bitwise_imm with li + bitwise_not

[Jeff Law]

https://gcc.gnu.org/g:51d09e67df52164c2025afa24531cf79820ff4c8

commit r14-4340-g51d09e67df52164c2025afa24531cf79820ff4c8
Author: Jivan Hakobyan <jivanhakobyan9@gmail.com>
Date:   Fri Sep 29 13:41:48 2023 -0600

    RISC-V: Replace not + bitwise_imm with li + bitwise_not
    
    In the case when we have C code like this
    
    int foo (int a) {
       return 100 & ~a;
    }
    
    GCC generates the following instruction sequence
    
    foo:
         not     a0,a0
         andi    a0,a0,100
         ret
    
    This patch replaces that with this sequence
    foo:
         li a5,100
         andn a0,a5,a0
         ret
    
    The profitability comes from an out-of-order processor being able to
    issue the "li a5, 100" at any time after it's fetched while "not a0, a0" has
    to wait until any prior setter of a0 has reached completion.
    
    gcc/ChangeLog:
            * config/riscv/bitmanip.md (*<optab>_not_const<mode>): New split
            pattern.
    
    gcc/testsuite/ChangeLog:
            * gcc.target/riscv/zbb-andn-orn-01.c: New test.
            * gcc.target/riscv/zbb-andn-orn-02.c: Likewise.

Diff:
---
 gcc/config/riscv/bitmanip.md                     | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c | 17 +++++++++++++++++
 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c | 17 +++++++++++++++++
 3 files changed, 46 insertions(+)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 0d126a8ece5..0f45bad14d0 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -215,6 +215,18 @@
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
 
+(define_insn_and_split "*<optab>_not_const<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+       (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
+              (match_operand:X 2 "const_arith_operand" "I")))
+  (clobber (match_scratch:X 3 "=&r"))]
+  "(TARGET_ZBB || TARGET_ZBKB) && !TARGET_ZCB
+   && !optimize_function_for_size_p (cfun)"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 3) (match_dup 2))
+   (set (match_dup 0) (bitmanip_bitwise:X (not:X (match_dup 1)) (match_dup 3)))])
+
 ;; '(a >= 0) ? b : 0' is emitted branchless (from if-conversion).  Without a
 ;; bit of extra help for combine (i.e., the below split), we end up emitting
 ;; not/srai/and instead of combining the not into an andn.
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c
new file mode 100644
index 00000000000..f9f32227bd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */
+
+int foo1(int rs1)
+{
+  return 100 & ~rs1;
+}
+
+int foo2(int rs1)
+{
+  return 100 | ~rs1;
+}
+
+/* { dg-final { scan-assembler-times "andn\t" 1 } } */
+/* { dg-final { scan-assembler-times "orn\t" 1 } } */
+/* { dg-final { scan-assembler-times "li\t" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c
new file mode 100644
index 00000000000..112c0fa968e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */
+
+int foo1(int rs1)
+{
+  return 100 & ~rs1;
+}
+
+int foo2(int rs1)
+{
+  return 100 | ~rs1;
+}
+
+/* { dg-final { scan-assembler-times "andn\t" 1 } } */
+/* { dg-final { scan-assembler-times "orn\t" 1 } } */
+/* { dg-final { scan-assembler-times "li\t" 2 } } */