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* [gcc r14-4472] Support smin/smax for V2HF/V4HF
@ 2023-10-08 13:04 hongtao Liu
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From: hongtao Liu @ 2023-10-08 13:04 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:91fdbd650d4bc3d1a13891095536f317e3a24d7a
commit r14-4472-g91fdbd650d4bc3d1a13891095536f317e3a24d7a
Author: liuhongt <hongtao.liu@intel.com>
Date: Thu Sep 21 16:00:57 2023 +0800
Support smin/smax for V2HF/V4HF
gcc/ChangeLog:
* config/i386/mmx.md (VHF_32_64): New mode iterator.
(<insn><mode>3): New define_expand, merged from ..
(<insn>v4hf3): .. this and
(<insn>v2hf3): .. this.
(movd_v2hf_to_sse_reg): New define_expand, splitted from ..
(movd_v2hf_to_sse): .. this.
(<code><mode>3): New define_expand.
gcc/testsuite/ChangeLog:
* gcc.target/i386/part-vect-vminmaxph-1.c: New test.
* gcc.target/i386/avx512fp16-64-32-vecop-1.c: Scan-assembler
only for { target { ! ia32 } }.
Diff:
---
gcc/config/i386/mmx.md | 74 +++++++++++++---------
.../gcc.target/i386/avx512fp16-64-32-vecop-1.c | 8 +--
.../gcc.target/i386/part-vect-vminmaxph-1.c | 36 +++++++++++
3 files changed, 83 insertions(+), 35 deletions(-)
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 3530615c706..6e6890c1458 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1943,25 +1943,7 @@
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_expand "<insn>v4hf3"
- [(set (match_operand:V4HF 0 "register_operand")
- (plusminusmult:V4HF
- (match_operand:V4HF 1 "nonimmediate_operand")
- (match_operand:V4HF 2 "nonimmediate_operand")))]
- "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
-{
- rtx op2 = gen_reg_rtx (V8HFmode);
- rtx op1 = gen_reg_rtx (V8HFmode);
- rtx op0 = gen_reg_rtx (V8HFmode);
-
- emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
- emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
-
- emit_insn (gen_<insn>v8hf3 (op0, op1, op2));
-
- emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
- DONE;
-})
+(define_mode_iterator VHF_32_64 [V2HF (V4HF "TARGET_MMX_WITH_SSE")])
(define_expand "divv4hf3"
[(set (match_operand:V4HF 0 "register_operand")
@@ -1983,39 +1965,50 @@
DONE;
})
+(define_mode_attr mov_to_sse_suffix [(V2HF "d") (V4HF "q")])
(define_expand "movd_v2hf_to_sse"
[(set (match_operand:V8HF 0 "register_operand")
(vec_merge:V8HF
(vec_duplicate:V8HF
(match_operand:V2HF 1 "nonimmediate_operand"))
- (match_operand:V8HF 2 "reg_or_0_operand")
+ (match_dup 2)
(const_int 3)))]
"TARGET_SSE"
{
- if (!flag_trapping_math && operands[2] == CONST0_RTX (V8HFmode))
+ if (!flag_trapping_math)
{
rtx op1 = force_reg (V2HFmode, operands[1]);
emit_move_insn (operands[0], lowpart_subreg (V8HFmode, op1, V2HFmode));
DONE;
}
+ operands[2] = CONST0_RTX (V8HFmode);
})
-(define_expand "<insn>v2hf3"
- [(set (match_operand:V2HF 0 "register_operand")
- (plusminusmult:V2HF
- (match_operand:V2HF 1 "nonimmediate_operand")
- (match_operand:V2HF 2 "nonimmediate_operand")))]
+(define_expand "movd_v2hf_to_sse_reg"
+ [(set (match_operand:V8HF 0 "register_operand")
+ (vec_merge:V8HF
+ (vec_duplicate:V8HF
+ (match_operand:V2HF 1 "nonimmediate_operand"))
+ (match_operand:V8HF 2 "register_operand")
+ (const_int 3)))]
+ "TARGET_SSE")
+
+(define_expand "<insn><mode>3"
+ [(set (match_operand:VHF_32_64 0 "register_operand")
+ (plusminusmult:VHF_32_64
+ (match_operand:VHF_32_64 1 "nonimmediate_operand")
+ (match_operand:VHF_32_64 2 "nonimmediate_operand")))]
"TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
{
rtx op2 = gen_reg_rtx (V8HFmode);
rtx op1 = gen_reg_rtx (V8HFmode);
rtx op0 = gen_reg_rtx (V8HFmode);
- emit_insn (gen_movd_v2hf_to_sse (op2, operands[2], CONST0_RTX (V8HFmode)));
- emit_insn (gen_movd_v2hf_to_sse (op1, operands[1], CONST0_RTX (V8HFmode)));
+ emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
+ emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
emit_insn (gen_<insn>v8hf3 (op0, op1, op2));
- emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
+ emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
DONE;
})
@@ -2030,15 +2023,34 @@
rtx op1 = gen_reg_rtx (V8HFmode);
rtx op0 = gen_reg_rtx (V8HFmode);
- emit_insn (gen_movd_v2hf_to_sse (op2, operands[2],
+ emit_insn (gen_movd_v2hf_to_sse_reg (op2, operands[2],
force_reg (V8HFmode, CONST1_RTX (V8HFmode))));
- emit_insn (gen_movd_v2hf_to_sse (op1, operands[1], CONST0_RTX (V8HFmode)));
+ emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
emit_insn (gen_divv8hf3 (op0, op1, op2));
emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
DONE;
})
+(define_expand "<code><mode>3"
+ [(set (match_operand:VHF_32_64 0 "register_operand")
+ (smaxmin:VHF_32_64
+ (match_operand:VHF_32_64 1 "nonimmediate_operand")
+ (match_operand:VHF_32_64 2 "nonimmediate_operand")))]
+ "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
+{
+ rtx op2 = gen_reg_rtx (V8HFmode);
+ rtx op1 = gen_reg_rtx (V8HFmode);
+ rtx op0 = gen_reg_rtx (V8HFmode);
+
+ emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
+ emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
+
+ emit_insn (gen_<code>v8hf3 (op0, op1, op2));
+
+ emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
+ DONE;
+})
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-64-32-vecop-1.c b/gcc/testsuite/gcc.target/i386/avx512fp16-64-32-vecop-1.c
index 754e909d77b..de883545d6d 100644
--- a/gcc/testsuite/gcc.target/i386/avx512fp16-64-32-vecop-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-64-32-vecop-1.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512fp16 -mavx512vl" } */
-/* { dg-final { scan-assembler-times "vaddph" 2 } } */
-/* { dg-final { scan-assembler-times "vsubph" 2 } } */
-/* { dg-final { scan-assembler-times "vmulph" 2 } } */
-/* { dg-final { scan-assembler-times "vdivph" 2 } } */
+/* { dg-final { scan-assembler-times "vaddph" 2 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-times "vsubph" 2 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-times "vmulph" 2 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-times "vdivph" 2 { target { ! ia32 } } } } */
#define DO_PRAGMA(X) _Pragma(#X)
diff --git a/gcc/testsuite/gcc.target/i386/part-vect-vminmaxph-1.c b/gcc/testsuite/gcc.target/i386/part-vect-vminmaxph-1.c
new file mode 100644
index 00000000000..ef215e62793
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/part-vect-vminmaxph-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -Ofast" } */
+/* { dg-final { scan-assembler-times {(?n)vmaxph[ \t].*%xmm[0-9]} 2 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-times {(?n)vminph[ \t].*%xmm[0-9]} 2 { target { ! ia32 } } } } */
+
+void
+foo16_max (_Float16* a, _Float16* b, _Float16* __restrict c)
+{
+ c[0] = __builtin_fmaxf16 (a[0], b[0]);
+ c[1] = __builtin_fmaxf16 (a[1], b[1]);
+}
+
+void
+foo32_max(_Float16* a, _Float16* b, _Float16* __restrict c)
+{
+ c[0] = __builtin_fmaxf16 (a[0], b[0]);
+ c[1] = __builtin_fmaxf16 (a[1], b[1]);
+ c[2] = __builtin_fmaxf16 (a[2], b[2]);
+ c[3] = __builtin_fmaxf16 (a[3], b[3]);
+}
+
+void
+foo16_min (_Float16* a, _Float16* b, _Float16* __restrict c)
+{
+ c[0] = __builtin_fminf16 (a[0], b[0]);
+ c[1] = __builtin_fminf16 (a[1], b[1]);
+}
+
+void
+foo32_min(_Float16* a, _Float16* b, _Float16* __restrict c)
+{
+ c[0] = __builtin_fminf16 (a[0], b[0]);
+ c[1] = __builtin_fminf16 (a[1], b[1]);
+ c[2] = __builtin_fminf16 (a[2], b[2]);
+ c[3] = __builtin_fminf16 (a[3], b[3]);
+}
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