[gcc r14-4484] rs6000: enable SImode in FP register on P7

[gcc r14-4484] rs6000: enable SImode in FP register on P7

[HaoChen Gui]

https://gcc.gnu.org/g:5cbe235de6d5c2a04a3116c6b6e63a0e4b8da304

commit r14-4484-g5cbe235de6d5c2a04a3116c6b6e63a0e4b8da304
Author: Haochen Gui <guihaoc@gcc.gnu.org>
Date:   Mon Oct 9 14:33:23 2023 +0800

    rs6000: enable SImode in FP register on P7
    
    gcc/
            PR target/88558
            * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
            Enable SImode on FP registers for P7.
            * config/rs6000/rs6000.md (*movsi_internal1): Add fmr for SImode
            move between FP registers.  Set attribute isa of stfiwx to "*"
            and attribute of stxsiwx to "p7".

Diff:
---
 gcc/config/rs6000/rs6000.cc |  2 +-
 gcc/config/rs6000/rs6000.md | 15 ++++++++-------
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index d10d22a5816..2828f01413c 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1904,7 +1904,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
 	  if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
 	    return 1;
 
-	  if (TARGET_P8_VECTOR && (mode == SImode))
+	  if (TARGET_POPCNTD && mode == SImode)
 	    return 1;
 
 	  if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 96084c1f47b..fa433ef0188 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7629,7 +7629,7 @@
 
 (define_insn "*movsi_internal1"
   [(set (match_operand:SI 0 "nonimmediate_operand"
-	  "=r,         r,
+	  "=r,         r,          d,
 	   r,          d,          v,
 	   m,          ?Z,         ?Z,
 	   r,          r,          r,          r,
@@ -7638,7 +7638,7 @@
 	   wa,         r,
 	   r,          *h,         *h")
 	(match_operand:SI 1 "input_operand"
-	  "r,          U,
+	  "r,          U,          d,
 	   m,          ?Z,         ?Z,
 	   r,          d,          v,
 	   I,          L,          eI,         n,
@@ -7651,6 +7651,7 @@
   "@
    mr %0,%1
    la %0,%a1
+   fmr %0,%1
    lwz%U1%X1 %0,%1
    lfiwzx %0,%y1
    lxsiwzx %x0,%y1
@@ -7674,7 +7675,7 @@
    mt%0 %1
    nop"
   [(set_attr "type"
-	  "*,          *,
+	  "*,          *,          fpsimple,
 	   load,       fpload,     fpload,
 	   store,      fpstore,    fpstore,
 	   *,          *,          *,          *,
@@ -7683,7 +7684,7 @@
 	   mtvsr,      mfvsr,
 	   *,          *,          *")
    (set_attr "length"
-	  "*,          *,
+	  "*,          *,          *,
 	   *,          *,          *,
 	   *,          *,          *,
 	   *,          *,          *,          8,
@@ -7692,9 +7693,9 @@
 	   *,          *,
 	   *,          *,          *")
    (set_attr "isa"
-	  "*,          *,
-	   *,          p8v,        p8v,
-	   *,          p8v,        p8v,
+	  "*,          *,          *,
+	   *,          p7,         p8v,
+	   *,          *,          p8v,
 	   *,          *,          p10,        *,
 	   p8v,        p9v,        p9v,        p8v,
 	   p9v,        p8v,        p9v,