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* [gcc r14-4487] Initial support for -mevex512
@ 2023-10-09 9:02 Haochen Jiang
0 siblings, 0 replies; only message in thread
From: Haochen Jiang @ 2023-10-09 9:02 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:6882df700cebf5a2292566c5acb2480f7dafd116
commit r14-4487-g6882df700cebf5a2292566c5acb2480f7dafd116
Author: Haochen Jiang <haochen.jiang@intel.com>
Date: Mon Oct 9 16:09:23 2023 +0800
Initial support for -mevex512
gcc/ChangeLog:
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_EVEX512_SET): New.
(OPTION_MASK_ISA2_EVEX512_UNSET): Ditto.
(ix86_handle_option): Handle EVEX512.
* config/i386/i386-c.cc
(ix86_target_macros_internal): Handle EVEX512. Add __EVEX256__
when AVX512VL is set.
* config/i386/i386-options.cc: (isa2_opts): Handle EVEX512.
(ix86_valid_target_attribute_inner_p): Ditto.
(ix86_option_override_internal): Set EVEX512 target if it is not
explicitly set when AVX512 is enabled. Disable
AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512.
* config/i386/i386.opt: Add mevex512. Temporaily RejectNegative.
Diff:
---
gcc/common/config/i386/i386-common.cc | 15 +++++++++++++++
gcc/config/i386/i386-c.cc | 7 ++++++-
gcc/config/i386/i386-options.cc | 19 ++++++++++++++++++-
gcc/config/i386/i386.opt | 4 ++++
4 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index 86596e96ad1..684b0451bb3 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -124,6 +124,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
#define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4
#define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
+#define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
@@ -311,6 +312,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
#define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4
#define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
+#define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
@@ -1358,6 +1360,19 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_mevex512:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_UNSET;
+ }
+ return true;
+
case OPT_mfma:
if (value)
{
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 47768fa0940..9c44bd7fb63 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -546,7 +546,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
if (isa_flag & OPTION_MASK_ISA_AVX512BW)
def_or_undef (parse_in, "__AVX512BW__");
if (isa_flag & OPTION_MASK_ISA_AVX512VL)
- def_or_undef (parse_in, "__AVX512VL__");
+ {
+ def_or_undef (parse_in, "__AVX512VL__");
+ def_or_undef (parse_in, "__EVEX256__");
+ }
if (isa_flag & OPTION_MASK_ISA_AVX512VBMI)
def_or_undef (parse_in, "__AVX512VBMI__");
if (isa_flag & OPTION_MASK_ISA_AVX512IFMA)
@@ -707,6 +710,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__SHA512__");
if (isa_flag2 & OPTION_MASK_ISA2_SM4)
def_or_undef (parse_in, "__SM4__");
+ if (isa_flag2 & OPTION_MASK_ISA2_EVEX512)
+ def_or_undef (parse_in, "__EVEX512__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index b9727d5f1f3..3398151b8e4 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -250,7 +250,8 @@ static struct ix86_target_opts isa2_opts[] =
{ "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 },
{ "-msm3", OPTION_MASK_ISA2_SM3 },
{ "-msha512", OPTION_MASK_ISA2_SHA512 },
- { "-msm4", OPTION_MASK_ISA2_SM4 }
+ { "-msm4", OPTION_MASK_ISA2_SM4 },
+ { "-mevex512", OPTION_MASK_ISA2_EVEX512 }
};
static struct ix86_target_opts isa_opts[] =
{
@@ -1112,6 +1113,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
IX86_ATTR_ISA ("sha512", OPT_msha512),
IX86_ATTR_ISA ("sm4", OPT_msm4),
IX86_ATTR_ISA ("apxf", OPT_mapxf),
+ IX86_ATTR_ISA ("evex512", OPT_mevex512),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
@@ -2577,6 +2579,21 @@ ix86_option_override_internal (bool main_args_p,
&= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM)
& ~opts->x_ix86_isa_flags_explicit);
+ /* Set EVEX512 target if it is not explicitly set
+ when AVX512 is enabled. */
+ if (TARGET_AVX512F_P(opts->x_ix86_isa_flags)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
+
+ /* Disable AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512. */
+ if (!TARGET_EVEX512_P(opts->x_ix86_isa_flags2))
+ {
+ opts->x_ix86_isa_flags
+ &= ~(OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512ER);
+ opts->x_ix86_isa_flags2
+ &= ~(OPTION_MASK_ISA2_AVX5124FMAPS | OPTION_MASK_ISA2_AVX5124VNNIW);
+ }
+
/* Validate -mpreferred-stack-boundary= value or default it to
PREFERRED_STACK_BOUNDARY_DEFAULT. */
ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index d4a7b7ec839..b5029b4ccb0 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1340,3 +1340,7 @@ mapx-inline-asm-use-gpr32
Target Var(ix86_apx_inline_asm_use_gpr32) Init(0)
Enable GPR32 in inline asm when APX_EGPR enabled, do not
hook reg or mem constraint in inline asm to GPR16.
+
+mevex512
+Target RejectNegative Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save
+Support 512 bit vector built-in functions and code generation.
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